Nanowire mesh FET with multiple threshold voltages
Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.
1. A field-effect transistor (FET), comprising:
a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and
a gate common to each of the device layers surrounding the nanowire channels.
2. The FET of claim 1 , wherein one or more of the device layers are configured to have a threshold voltage V t1 and one or more other of the device layers are configured to have a threshold voltage V t2 , and wherein the one or more device layers configured to have the threshold voltage V t1 have nanowire channels with at least one of a width and a thickness that is less than a width and thickness of the nanowire channels in the device layers configured to have the threshold voltage V t2 .
3. The FET of claim 2 , wherein V t1 is greater than V t2 .
4. The FET of claim 2 , wherein the nanowire channels of the one or more device layers configured to have the threshold voltage V t1 each have a width of from about one nm to about 10 nm.
5. The FET of claim 2 , wherein the nanowire channels of the one or more device layers configured to have the threshold voltage V t1 each have a thickness of from about one nm to about 10 nm.
6. The FET of claim 2 , wherein the nanowire channels of the one or more device layers configured to have the threshold voltage V t2 each have a width of from about five nm to about 20 nm.
7. The FET of claim 2 , wherein the nanowire channels of the one or more device layers configured to have the threshold voltage V t2 each have a thickness of from about five nm to about 20 nm.
8. The FET of claim 1 , wherein the source and drain regions of each of the device layers are doped with an n-type or p-type dopant.
9. The FET of claim 1 , wherein the nanowire channels of each of the device layers are undoped.
10. The FET of claim 1 , wherein the gate is separated from the nanowire channels by a dielectric.
11. The FET of claim 10 , wherein the dielectric comprises SiO 2 .
12. The FET of claim 1 , further comprising spacers between the source and drain regions of the device layers and the gate.
13. The FET of claim 12 , wherein the spacers comprise SiN.
14. The FET of claim 1 , wherein the gate comprises one or more of polysilicon and a metal.
15. The FET of claim 1 , wherein the gate comprises metal polysilicon.