IP Library › Granted Patent US 8,477,225
Granted Patent B2
US 8,477,225 · App. 12/481,436 · Granted Jul 2, 2013

Method and apparatus providing pixel array having automatic light control pixels and image capture pixels

Inventor: Jorgen Moholt (Moss, NO)
Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 8,477,225
App. No.
12/481,436
Granted
Jul 2, 2013
Kind
B2
Abstract

A pixel array uses two sets of pixels to provide accurate exposure control. One set of pixels provide continuous output signals for automatic light control (ALC) as the other set integrates and captures an image. ALC pixels allow monitoring of multiple pixels of an array to obtain sample data indicating the amount of light reaching the array, while allowing the other pixels to provide proper image data. A small percentage of the pixels in an array is replaced with ALC pixels and the array has two reset lines for each row; one line controls the reset for the image capture pixels while the other line controls the reset for the ALC pixels. In the columns, at least one extra control signal is used for the sampling of the reset level for the ALC pixels, which happens later than the sampling of the reset level for the image capture pixels.

Claims (31)

1. A pixel array comprising:

a plurality of image capture pixels in a pixel row for providing image capture signals, each of said plurality of image capture pixels configured to transfer charge to a corresponding charge storage region after an integration period;

at least one automatic light control pixel in said pixel row for providing an automatic light control signal, said at least one automatic light control pixel configured to transfer charge to a corresponding charge storage region during said integration period;

a first reset line for resetting said charge storage regions of said plurality of image capture pixels; and

a second reset line for resetting said charge storage region of said at least one automatic light control pixel.

2. The pixel array of claim 1 , wherein each of said plurality of image capture pixels comprises at least a photo sensor, said charge storage region, and a reset transistor connected to said first reset line.

3. The pixel array of claim 1 , wherein said at least one automatic light control pixel comprises at least a photosensor for providing charge to said charge storage region during said integration period, and a reset transistor connected to said second reset line for resetting said charge storage region.

4. The pixel array of claim 3 , wherein said at least one automatic light control pixel is configured to continuously transfer charge to said corresponding charge storage region during said integration period.

5. The pixel array of claim 1 further comprising a control circuit for providing a first reset signal on said first reset line at a different time than providing a second reset signal on said second reset line.

6. The pixel array of claim 5 , wherein said plurality of image capture pixels have different integration times than said at least one automatic light control pixel.

7. The pixel array of claim 1 , wherein said at least one automatic light control pixel has a calculated output voltage with an applied gain factor, based on a ratio of an average output voltage of a group of said plurality of image capture pixels surrounding said automatic light control pixel to an average output voltage of said automatic light control pixel.

8. The pixel array of claim 1 , wherein said at least one automatic light control pixel comprises a photosensor directly coupled to said charge storage region.

9. The pixel array of claim 1 , wherein said at least one automatic light control pixel comprises a photosensor and a transfer transistor connected between said photosensor and said charge storage region, said transfer transistor configured to transfer charge to said charge storage region during at least a portion of said integration period.

10. A pixel array comprising:

a plurality of image capture pixels, wherein each image capture pixel has a transfer transistor between a photosensor and a floating diffusion region for transferring charge at the end of an integration period;

a plurality of automatic light control pixels, wherein each automatic light control pixel is configured to transfer charge from a photosensor to a floating diffusion region of said automatic light control pixel during said integration period;

a first reset line for resetting said plurality of image capture pixels; and

a second reset line for resetting said plurality of automatic light control pixels.

11. The pixel array of claim 10 , further comprising a control circuit for providing a first reset signal on said first reset line at a different time than providing a second reset signal on said second reset line.

12. The pixel array of claim 11 , wherein said plurality of automatic light control pixels has a different integration time than said plurality of image capture pixels.

13. The pixel array of claim 11 , wherein said one of said plurality of automatic light control pixels has a calculated output voltage with an applied gain factor, based on a ratio of an average output voltage of a group of said plurality of image capture pixels surrounding said automatic light control pixel to an average output voltage of said automatic light control pixel.

14. The pixel array of claim 10 , wherein said photosensor of each automatic light control pixel is directly coupled to said charge storage region.

15. The pixel array of claim 10 , wherein each automatic light control pixel comprises a transfer transistor connected between said photosensor and said floating diffusion region, said transfer transistor configured to transfer charge to said charge storage region during at least a portion of said integration period.

16. The pixel array of claim 15 , wherein said transfer transistor is configured to continuously transfer charge to said charge storage region during said integration period.

17. A method of controlling an imager comprising an array of pixels, said method comprising the acts of:

operating a first set of pixels in the array to obtain a set of image capture pixel signals during an integration period;

capturing an image signal with said set of image capture pixel signals using a sample-and-hold circuit;

operating a second set of pixels in the array to obtain a set of light control pixel signals, wherein said step of operating said second set of pixels includes connecting a photosensor of each of said second set of pixels to a respective charge collection region of said second set of pixels during said integration period;

capturing said set of light control pixel signals using said sample-and-hold circuit; and

performing automatic light control with said set of light control pixel signals,

wherein said step of connecting said photosensor to said respective charge collection region of said second set of pixels during said integration period further comprises activating a transfer transistor during at least a portion of said integration period, wherein said transfer transistor is configured to prevent transfer of charge from said photosensor to said charge collection region when not activated.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Priority Claims (1)
GB 0517804.1 · Sep 1, 2005 · national
Continuity (2)
Continuation 11223045 · Sep 12, 2005
Related Publication 20090244348A1 · Oct 1, 2009