IP Library › Granted Patent US 8,486,611
Granted Patent B2
US 8,486,611 · App. 12/836,495 · Granted Jul 16, 2013

Semiconductor constructions and methods of forming patterns

Inventors: Dan Millward (Boise, ID); Kaveri Jain (Boise, ID); Zishu Zhang (Boise, ID); Lijing Gou (Boise, ID); Anton de Villiers (Boise, ID); Jianming Zhou (Boise, ID); Yuan He (Boise, ID); Michael Hyatt (Boise, ID); Scott L. Light (Boise, ID)
Assignee: Micron Technology, Inc.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,486,611
App. No.
12/836,495
Granted
Jul 16, 2013
Kind
B2
Abstract

Some embodiments include methods of forming patterns. A semiconductor substrate is formed to comprise an electrically insulative material over a set of electrically conductive structures. An interconnect region is defined across the electrically conductive structures, and regions on opposing sides of the interconnect region are defined as secondary regions. A two-dimensional array of features is formed over the electrically insulative material. The two-dimensional array extends across the interconnect region and across the secondary regions. A pattern of the two-dimensional array is transferred through the electrically insulative material of the interconnect region to form contact openings that extend through the electrically insulative material and to the electrically conductive structures, and no portions of the two-dimensional array of the secondary regions is transferred into the electrically insulative material.

Claims (61)

1. A method of forming patterns, the method comprising:

forming a first and second masking materials over an electrically insulative material, the second masking material being over the first masking material;

forming a trench extending through the first and second masking materials and to an upper surface of the electrically insulative material, with said trench passing across a set of electrically conductive lines underlying the electrically insulative material;

forming a plurality of openings in the second masking material on opposing sides of the trench, with said openings not passing through the first masking material; the openings being aligned with one another to define a plurality of columns; adjacent openings within each individual column being spaced from one another by a uniform spacing interval; the trench defining an interconnect region;

treating surface regions at the bottoms of the openings to render such surface regions selectively wettable by one block of a block copolymer relative to another block of the block copolymer;

after said treatment, removing the second masking material to leave the treated surface regions defining an initial part of a two-dimensional array that extends across the first masking material and the electrically insulative material, the treated surface regions of the initial part of the two-dimensional array being on opposing sides of the trench;

forming the block copolymer over the first masking material and the electrically insulative material, and then inducing self-assembly of the block copolymer in an epitaxial process in which a pattern from the treated surface regions is propagated through the self-assembled block copolymer to form the two-dimensional array from first domains of the self-assembled block copolymer; with the two-dimensional array extending across the trench; and

removing the first domains to leave openings extending to the electrically insulative material in the interconnect region.

2. The method of claim 1 further comprising forming a brush layer between the first and second masking layers.

3. The method of claim 1 further comprising:

extending the openings through the electrically insulative material and to the electrically conductive lines; and

forming electrically conductive material within the openings to form electrical contacts extending through the electrically insulative material and to the electrically conductive lines.

4. The method of claim 1 wherein the treating comprises depositing a layer within the openings and over the first masking material at the bottoms of the openings.

5. The method of claim 1 wherein the treating comprises chemically modifying the first masking material at the bottoms of the openings.

6. A method of forming patterns, the method comprising:

forming a first masking material over a substrate;

forming a second masking material over the first masking material, the second masking material being patterned to have a trench formed therein, and to have a plurality of openings therein on opposing sides of the trench; the openings being aligned with one another to define a plurality of columns; adjacent openings within each individual column being spaced from one another by a uniform spacing interval; the trench defining an interconnect region over the substrate;

transferring the pattern from the second masking material through the first masking material to extend the openings and the trenched interconnect region to the substrate;

after transferring the pattern through the first masking material, forming structures within the openings;

after forming the structures within the openings, removing the second masking material to leave the structures; the structures being arranged in the pattern of columns defined by the openings; the structures defining an initial part of a two-dimensional array that extends across the substrate, the structures of the initial part of the two-dimensional array being on opposing sides of the trenched interconnect region; the structures having uppermost surfaces;

forming a fill material between the structures to a depth which leaves the uppermost surfaces of the structures exposed;

forming block copolymer across the structures and the fill material, and then inducing self-assembly of the block copolymer; the self-assembled block copolymer having first and second domains, the first domains being in the form of features arranged in the two-dimensional array; with the two-dimensional array extending across the trenched interconnect region, some of the features being directly over the uppermost surfaces of the structures, and some of the features being directly over the interconnect region;

selectively removing the first domains relative to the second domains to leave a pattern of contact openings across the interconnect region; and

extending the contact openings through the fill material and into the substrate.

7. The method of claim 6 wherein the fill material is neutral wetting relative to the blocks of the block copolymer.

8. The method of claim 6 wherein the uppermost surfaces are preferential wetting relative to a first block of the block copolymer, and wherein the fill material is preferential wetting relative to a second block of the block copolymer which is different from the first block of the block copolymer.

9. The method of claim 6 wherein the substrate comprises insulative material over conductive structures, and further comprising:

extending the contact openings through the electrically insulative material and to the conductive structures; and

forming electrically conductive material within the contact openings to form electrical contacts extending through the insulative material and to the conductive structures.

10. The method of claim 6 wherein the second masking material comprises photoresist, and wherein the first masking material comprises silicon nitride or silicon oxynitride.

11. The method of claim 6 wherein the forming the structures within the openings comprises:

forming a layer to a thickness such that the layer fills the openings and lines the trench; and

utilizing an etch to remove the layer from within the trench while leaving the layer within the openings as the structures.

12. The method of claim 11 wherein the layer comprises silicon dioxide.

13. The method of claim 11 wherein the etch is a fluorine-containing wet etch.

14. A method of forming a pattern using a block copolymer having an inherent periodicity of L 0 , the method comprising:

forming a semiconductor substrate to comprise an electrically insulative material over a set of parallel electrically conductive lines, the lines being spaced along a pitch of about

1

2

⁢

L

0

;

forming a first masking material over the electrically insulative material;

forming a second masking material over the first masking material, the second masking material being patterned to have a trench formed therein which passes across the set of electrically conductive lines, and to have a plurality of openings therein on opposing sides of the trench; the openings being aligned with one another to define a plurality of columns, with the columns on one side of the trench being offset from those on the other side of the trench by a center-to-center distance of about

1

2

⁢

L

0

;

 adjacent openings within each individual column being spaced center-to-center by about √{square root over (3)}L 0 ; the trench defining an interconnect region;

transferring the pattern from the second masking material into the first masking material to transfer the trench into the first masking material;

after transferring the pattern into the first masking material, forming structures within the openings;

after forming the structures within the openings, removing the second masking material to leave the structures; the structures being arranged in the pattern of columns defined by the openings; the structures defining an initial part of a two-dimensional array that extends across the electrically insulative material, the structures of the initial part of the two-dimensional array being on opposing sides of the trench;

forming the block copolymer adjacent the structures, and inducing self-assembly of the block copolymer; the self-assembled block copolymer having first and second domains, the first domains being in the form of features that complete the two-dimensional array, and the second domains at least partially surrounding the first domains; with the two-dimensional array extending across the trench in the first masking material;

selectively removing the first domains relative to the second domains to leave openings extending to the electrically insulative material in the interconnect region, and to leave openings extending to the masking material in regions other than the interconnect region;

using an etch selective for the electrically insulative material relative to the masking material to extend the openings in the interconnect region through the electrically insulative material and to thereby form contact openings to the electrically conductive lines; and

forming electrically conductive material within the contact openings to form electrical contacts extending through the electrically insulative material and to the electrically conductive lines.

15. The method of claim 14 wherein the first domains are cylinders extending normal to an upper surface of the electrically insulative material.

16. The method of claim 14 wherein the first and second domains are arranged in a pattern of hexagonally closest packed unit cells.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2010
From: MILLWARD, DAN; JAIN, KAVERI; ZHANG, ZISHU; GOU, LIJING; DEVILLIERS, ANTON; ZHOU, JIANMING; HE, YUAN; HYATT, MICHAEL; LIGHT, SCOTT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 024685/0911 →
Continuity (1)
Related Publication 20120015486A1 · Jan 19, 2012