Surrounding stacked gate multi-gate FET structure nonvolatile memory device
Nonvolatile memory devices having a low off state leakage current and an excellent data retention time characteristics. The present invention provides a surrounding stacked gate fin field effect transistor nonvolatile memory structure comprising a silicon-on-insulator substrate of a first conductivity type and a fin active region projecting from an upper surface of the insulator. The structure further includes a tunnel oxide layer formed on the fin active region and a first gate electrode disposed on the tunnel oxide layer and upper surface of the insulator. Additionally, the structure includes an oxide/nitride/oxide (ONO) composite layer formed on the first gate electrode, a second gate electrode formed on the ONO composite layer and patterned so as to define a predetermined area of the ONO composite layer. The structure further includes a dielectric spacer formed on a sidewall of the second gate electrode and source/drain regions formed in the fin active region on both sides of the second gate electrode.
1. A nonvolatile memory device having a surrounding stacked gate fin FET, the device comprising:
a silicon-on-insulator (SOI) substrate being characterized by a first conductivity type, the substrate including an upper surface;
a fin active region projecting from the upper surface of the substrate;
a tunnel oxide layer overlying the fin active region;
a first gate electrode disposed on the tunnel oxide layer and upper surface of the substrate;
a dielectric composite layer formed on the surface of the first gate electrode;
a second gate electrode formed on a top surface and side surfaces of the dielectric composite layer and patterned so as to define a stacked gate structure including the second gate electrode, the dielectric composite layer, the first gate electrode, and the tunnel oxide layer;
a dielectric spacer formed on sidewalls of the stacked gate electrodes structure;
source/drain regions formed in the fin active region on both sides of the second gate electrode; and
elevated source/drain regions overlying the respective source/drain regions, wherein the elevated source/drain regions have a top surface that is substantially coplanar with a top surface of the second gate electrode.
2. The device of claim 1 , wherein the first gate electrode is formed by an in-situ doped polysilicon material doped with a second conductive impurity.
3. The device of claim 1 , wherein the tunnel oxide layer has a thickness in the range from 20 Å to 80 Å.
4. The device of claim 1 , wherein the dielectric composite layer comprises oxide/nitride/oxide and has a thickness in the range of about from 20Å to 100Å.
5. The device of claim 1 , wherein the first gate electrode is structured to function as a floating gate configured to store data by trapping electrons when a program voltage is applied to the second gate electrode.
6. The device of claim 1 , wherein the second gate electrode is structured to function as a control gate configured to turn on a channel of the fin FET when a control voltage is applied to the second gate electrode.
7. The device of claim 5 , wherein the program voltage is higher than a voltage applied to a drain region.
8. The device of claim 1 , wherein the dielectric spacer is composed of an oxide/nitride composite layer.
9. The device of claim 1 , wherein the source/drain regions are doped with phosphorus ions.
10. The device of claim 1 , wherein the fin active region has a height that is about 1000 Å to about 3000 Å from the upper surface of the substrate.
11. The device of claim 1 , wherein the first gate electrode has a thickness in the range from 100 Å to 500 Å.
12. The device of claim 1 , wherein the second gate electrode has a thickness in the range from 500 Å to 4000 Å.