Method and apparatus for rate matching within a communication system
A method and apparatus for rate matching is described. During operation of a transmitter, multiple data streams are received and individually interleaved with a permutation of a same length K Π . A permutation (π p0 ) of a second stream is the same as a permutation (π sys ) of a first stream and a permutation (π p1 ) of a third stream is different from the permutation of the first stream. Each element of π p1 is derived from the corresponding element of π sys . The plurality of interleaved streams are multiplexed to form a circular buffer. Finally, data is transmitted from the circular buffer.
1. An apparatus comprising:
an encoder outputting a plurality of data streams; wherein the encoder is a turbo encoder employing Quadratic permutation polynomial interleaver;
interleaving circuitry individually interleaving each data stream to form a first, second, and third interleaved stream with each stream formed by using a permutation of a same length K Π , wherein a permutation (π p0 ) used to form the second interleaved stream is the same as a permutation (π sys ) used to form the first interleaved stream and a permutation (π p1 ) used to form the third interleaved stream is different from π sys , and each element of π p1 is derived from the corresponding element of π sys ;
bit-collection circuitry multiplexing the interleaved streams to form a circular buffer; and
transmission circuitry transmitting bits from the circular buffer;
wherein the bit-collection circuitry forms the circular buffer by:
interlacing the interleaved second stream and interleaved third stream to form an intermediate stream; and
concatenating the interleaved first stream with the intermediate stream.
2. The apparatus of claim 1 wherein the Quadratic permutation polynomial interleaver has even-even property that maps all even positions in the input to all even positions in the output.
3. The apparatus of claim 1 wherein each element of the permutation π p1 is derived from a corresponding element of π sys via function π p1 (i)=f(π sys (i),δ 1 ), 0≦i≦K Π , where δ 1 is an integer.
4. The apparatus of claim 1 wherein each element of π p1 is derived from a corresponding element of π sys via function π p1 (i)=(π sys (i)+δ 1 ) % K Π , 0≦i<K Π , where δ 1 is an integer.
5. The apparatus of claim 4 wherein δ 1 =1.
6. The apparatus of claim 1 wherein the transmitting circuitry
receives a redundancy version (RV) and a number of desired bits; and
transmits the number of desired bits from the circular buffer starting at the RV position.
7. The apparatus of claim 6 wherein the redundancy version results in a portion of the first stream not being transmitted.
8. The apparatus of claim 6 wherein the transmitting circuitry transmits the number of desired bits from position R×(N col ×RV idx +σ) of the circular buffer, wherein RV idx is an integer denoting the redundancy version, and σ, R and N col are integers.
9. The apparatus of claim 1 wherein the first data stream comprises a systematic stream, the second data stream comprises a first parity stream, and the third data stream comprises a second parity stream.
10. The apparatus of claim 1 where the step of interleaving comprises the step of interleaving via a sub-block interleaver.
11. The apparatus of claim 1 wherein the step of individually interleaving each data stream comprises the step of adding dummy bits to each data stream before individually interleaving so that each stream has length K Π .
12. The apparatus of claim 1 wherein the transmitting circuitry outputs consecutive bits from the circular buffer.