Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods

1. A stacked system of microelectronic die packages, comprising:

a first die package including a first die and a first dielectric casing at least partially covering the first die, first lateral sides along the first dielectric casing, and first metal contacts having first lateral contact surfaces along the first lateral sides of the first dielectric casing;

a second die package including a second die and a second dielectric casing at least partially covering the second die, second lateral sides along the second dielectric casing, and second metal contacts having second lateral contact surfaces along the second lateral sides of the second dielectric casing, wherein the second die package is stacked on top of the first die package and the first metal contacts are at least generally aligned with corresponding second metal contacts;

a third die package including a third die and a third dielectric casing at least partially covering the third die, third lateral sides along the third dielectric casing, and third metal contacts having third lateral contact surfaces along the third lateral sides of the third dielectric casing wherein the third metal contacts are at least generally aligned with corresponding first metal contacts; and

metal solder connectors including first-set connectors and second-set connectors, wherein the first-set connectors are coupled to individual first metal contacts and individual second metal contacts, and wherein the second-set connectors are coupled to individual first metal contacts and individual third metal contacts, and wherein at least a portion of the first-set connectors contacts the first and second lateral contact surfaces, and wherein at least a portion of the second-set connectors contacts the first and third lateral contact surfaces, and wherein the first-set connectors are physically and electrically isolated from the individual third metal contacts while the second-set connectors are physically and electrically isolated from the individual second metal contacts.

2. The stacked system of claim 1 , wherein at least a portion of the first-set connectors projects laterally outward from the lateral contact surfaces of the first and second casings.

3. The stacked system of claim 1 , wherein the first-set connectors further project laterally inward between the first die package and the second die package.

4. The stacked system of claim 1 , wherein the first metal contacts further include first top-side contact surfaces and first bottom-side contact surfaces, the second metal contacts further include second top-side contact surfaces and second bottom-side contact surfaces, and wherein individual metal solder connectors of the first-set connectors are further coupled to one of the first top-side surfaces and a corresponding one of the second bottom-side surfaces.

5. The stacked system of claim 1 , wherein the first die has a first lateral dimension and the second die has a second lateral dimension different than the first lateral dimension, and wherein the first and second casings have equal lateral dimensions.

6. A computing system, comprising at least one of a processor, a memory, and an input/device, wherein the computing system includes the stacked system according to claim 1 .

7. A stacked system of microelectronic die packages, comprising:

a first die package having a first lateral edge and first metal leads having first contact surfaces flush with the first lateral edge;

a second die package having a second lateral edge and second metal leads having second contact surfaces flush with the second lateral edge, wherein the second contact surfaces are generally aligned with the first lateral contact surfaces;

a third die package having a third lateral edge and third metal leads having third contact surfaces flush with the third lateral edge, wherein the third contact surfaces are generally aligned with the first lateral contact surfaces; and

external electrically conductive inter-package connectors, including first-set connectors and second-set connectors, wherein the individual first-set connectors are connected to one of the first contact surfaces and a corresponding second contact surface, and wherein the first-set connectors comprise individual metal solder lines that bridge a first gap between the first die package and the second die package, and wherein the individual second-set connectors are connected to one of the first contact surfaces and a corresponding third contact surface, and wherein the second-set connectors comprise individual metal solder lines that bridge a second gap between the first die package and the third die package, and wherein the first-set connectors are physically and electrically isolated from the corresponding third contact surface while the second-set connectors are physically and electrically isolated from the corresponding second contact surface.

8. The stacked system of claim 7 , wherein the first gap spans a lateral distance of up to 60 microns.

9. The stacked system of claim 7 , wherein the first die package comprises a first dielectric material that is configured to separate the individual first metal leads apart from each other, and wherein the second die package comprises a second dielectric material that is configured to separate the individual second metal leads apart from each other.

10. The stacked system of claim 9 , wherein the first dielectric material has a top-side surface that is configured so that the individual first metal leads are coupled with a top-side of the first die package.

11. The stacked system of claim 9 , wherein the second dielectric material has a bottom-side surface that is configured so that the individual second metal leads are coupled with a bottom-side of the second die package.

12. A microelectronic device, comprising:

a molded dielectric material having lateral-side, bottom-side, and top-side surfaces;

a die at least partially encapsulated within the dielectric material and spaced laterally apart from the lateral surface of the dielectric material; and

individual metal leads electrically coupled with the die and the individual metal leads having a wetting surface configured for attaching external inter-package solder lines, wherein the wetting surface includes an exposed metal portion that is flush with the lateral surface of the dielectric material and at least one of the top-side and bottom-side surfaces of the dielectric material, and wherein the external inter-package solder lines include first-set solder lines and second-set solder lines;

wherein the first-set solder lines are coupled to a first external device while the second-set solder lines are coupled to a second external device, and wherein the first-set connectors are physically and electrically isolated from the second external device while the second-set connectors are physically and electrically isolated from the first external device.

13. The microelectronic device of claim 12 , further comprising a dielectric spacer layer coupled to a bottom side of the die for electrically isolating active features of the die.

14. The microelectronic device of claim 13 , further comprising metal traces for coupling the metal leads to the active features.

15. The microelectronic device of claim 14 , wherein the metal traces are configured to selectively electrically couple integrated circuitry of the die with the metal leads.

16. The microelectronic device of claim 12 , wherein the top-side surface of the dielectric material is substantially planar for package-to-package stacking.

17. The microelectronic device of claim 12 , wherein the metal leads have a lateral thickness that is at least 650 microns.

18. The microelectronic device of claim 12 , wherein the dielectric material has a lateral thickness that is at least 650 microns.