Thermally enhanced structure for multi-chip device
A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved.
1. A structure comprising:
a heat sink block having a first surface attached to a first semiconductor die;
the first semiconductor die coupled to a second semiconductor die;
an encapsulation material layer on at least one of the first semiconductor die and the second semiconductor die;
a redistribution layer formed on the encapsulation material layer and coupled to the second semiconductor die; and
a plurality of thermal vias coupled to a second surface of the heat sink block, wherein the thermal vias are embedded in the encapsulation material layer.
2. The structure of claim 1 , wherein the heat sink block is attached to a backside surface of the first semiconductor die.
3. The structure of claim 1 , wherein the heat sink block is attached to a front side surface of the first semiconductor die, and wherein the heat sink block has a plurality of openings.
4. The structure of claim 1 , further comprising:
a plurality of copper pillars coupled between the second semiconductor die and the redistribution layer.
5. The structure of claim 1 , further comprising:
a second heat sink block placed between the heat sink block and the redistribution layer;
and
a solder ball placed underneath the redistribution layer.
6. The structure of claim 1 , further comprising:
a third semiconductor die placed between the first semiconductor die and the second semiconductor die; and
a plurality of bumps placed between the first semiconductor die and the third semiconductor die.
7. The structure of claim 1 , further comprising:
a second redistribution layer formed between the second semiconductor die and the encapsulation material layer.