Memory network methods, apparatus, and systems
Apparatus and systems may include a first node group include a first network node coupled to a memory, the first network node including a first port, a second port, a processor port, and a hop port. Network node group may include a second network node coupled to a memory, the second network node including a first port, a second port, a processor port, and a hop port, the hop port of the second network node coupled to the hop port of the first network node and configured to communicate between the first network node and the second network node. Network node group may include a processor coupled to the processor port of the first network node and coupled to the processor port of the second network node, the processor configured to access the first memory through the first network node and the second memory through the second network node. Other apparatus, systems, and methods are disclosed.
1. An apparatus comprising:
a first node group including:
a first network node coupled to a first memory, the first network node including a first port, a second port, a processor port, and a hop port;
a second network node coupled to a second memory, the second network node including a first port, a second port, a processor port, and a hop port, the hop port of the second network node coupled to the hop port of the first network node providing a hop path, the hop port of the second network node and the hop port of the first network node configured to communicate between the first network node and the second network node such that a request at the first network node, for data not in the first network node and not in the first memory coupled to the first network node, is automatically sent via the hop path to the second network node prior to being sent to another node group if the data is not in the second network node and not in the second memory coupled to the second network node; and
a processor coupled to the processor port of the first network node and coupled to the processor port of the second network node, the processor configured to access the first memory through the first network node and the second memory through the second network node.
2. The apparatus of claim 1 , configured to communicatively couple to a second node group, the second node group comprising:
a third network node coupled to a memory, the third network node including a first port, a second port, a processor port, and a hop port;
a fourth network node coupled to a memory, the fourth network node including a first port, a second port, a processor port, and a hop port, the hop port of the fourth network node coupled to the hop port of the third network node; and
a second processor coupled to the third network node using the processor port of the third network node and coupled to the fourth network node using the processor port of the fourth network node, wherein one of the first and second ports of the third network node is coupled to one of the first and second ports of the first network node.
3. The apparatus of claim 1 , wherein the memory coupled to the first network node comprises at least one Dynamic Random Access Memory (DRAM) array.
4. The apparatus of claim 1 , wherein the first network node comprises an input/output driver circuit.
5. The apparatus of claim 1 , wherein the first network node and the memory coupled to the first network node are disposed in a single package.
6. The apparatus of claim 1 , wherein the first network node, the memory coupled to the first network node and the processor coupled to the first network node are disposed in a single package.
7. The apparatus of claim 1 , wherein the second network node and the memory coupled to the second network node is disposed in a single package.
8. The apparatus of claim 1 , wherein the second network node, the memory coupled to the second network node and the processor coupled to the second network node are disposed in a single package.
9. The apparatus of claim 1 , wherein the first network node is configured to perform Error Check and Correction (ECC) during data communication between the first memory and the first processor.
10. The apparatus of claim 1 , wherein the memory coupled to the first network node comprises a NAND flash memory array.
11. The apparatus of claim 1 , wherein the memory coupled to the first network node comprises a NOR flash memory array.
12. The apparatus of claim 1 , wherein the processor coupled to the first network node comprises a single-core processor.
13. The apparatus of claim 1 , wherein the processor coupled to the first network node comprises a multi-core processor.
14. The apparatus of claim 1 , wherein the processor coupled to the first network node is a single core of a multi-core processor.
15. The apparatus of claim 1 , wherein the processor coupled to the first network node comprises an Application Specific Integrated Circuit (ASIC).
16. The apparatus of claim 1 , wherein the processor coupled to the first network node comprises a substrate with embedded processors.
17. The apparatus of claim 1 , wherein the apparatus includes a memory network in which the first node group and associated memories are disposed, the memory network structured to operate with a single set of addresses in the network.