Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures

1. A method for semiconductor processing, comprising:

forming self-aligned tiered elongated mandrel structures having n tiers over a substrate, where n≧2, wherein mandrels at tier n are disposed over mandrels at tier n−1, wherein a distance between immediately adjacent mandrels at tier n is greater than a distance between adjacent mandrels at tier n−1, wherein the mandrels at tier n have exposed top surfaces, wherein mandrels at each tier are formed of a different material than mandrels at immediately adjacent tiers, wherein forming self-aligned tiered elongated mandrel structures comprises:

forming a pattern in a photoresist layer, the pattern comprising photoresist features having a photoresist feature width;

etching the pattern into two or more layers of the different materials corresponding to the tiers of the mandrel structure, the etched layers comprising etched features underlying the photoresist features and having a width substantially equal to the photoresist feature width; and

subsequently reducing dimensions of etched features of the layer at tier n to form the mandrels at tier n;

providing a layer of spacer material on the tiered mandrel structures; and

subjecting the spacer material to an etch to simultaneously define spacers on sidewalls of each of the tiers.

2. The method of claim 1 , wherein providing the tiered elongated mandrel structures comprises providing tier n substantially centered across the width of tier n−1.

3. The process of claim 1 , wherein reducing dimensions removes the upper film over some sections of the substrate, thereby leaving an entire width of the lower film exposed over those sections.

4. The process of claim 1 , further comprising forming photolithographically defined features for forming bond pads, the photolithographically defined features in contact with some of the spacers.

5. The process of claim 1 , wherein the pattern comprises lines of varying widths, the lines defining tiers of the tiered elongated mandrel structures.

6. The process of claim 1 , wherein forming the pattern comprises forming a window section between adjacent segments of the lower film to increase separation of spacers formed on a mandrel tier defined by the lower film in the window section relative to a separation of spacers formed on the mandrel tier defined by the lower film in other sections of the pattern.

7. The process of claim 6 , wherein the window section comprises adjacent windows permitting lateral separation of spacers sufficient to enable non-pitch multiplied contacts to features defined by the spacers.

8. The method of claim 1 , further comprising selectively removing at least portions of the tiered elongated mandrel structures relative to the spacers to form a spacer pattern defined by the spacers.

9. The method of claim 8 , further comprising transferring the spacer pattern to the substrate.

10. The method of claim 9 , wherein transferring the spacer pattern to the substrate comprises etching the substrate to define trenches.

11. The method of claim 10 , wherein etching the substrate to define trenches defines interconnect lines in a partially fabricated memory device.

12. The method of claim 1 , further comprising providing one or more hard mask layers between the substrate and the mandrel structures.

13. A method for semiconductor processing, comprising:

providing a self-aligned tiered mandrel structure over a substrate, the tiered mandrel structure having a first elongated mandrel tier underlying a second elongated mandrel tier, the first elongated mandrel tier having a first width, the second mandrel having a second width smaller than the first width, wherein an uppermost tier of the mandrel structure has exposed top surfaces, wherein the first elongated mandrel tier and the second elongated mandrel tier are formed of different materials, wherein providing the self-aligned tiered mandrel structure comprises:

providing a pattern in a masking layer;

transferring the pattern into first and second layers of the different materials corresponding to the first and second elongated mandrel tiers of the mandrel structure; and

subsequently reducing dimensions of patterned features of the second layer to form the second mandrel in the second layer; and

simultaneously defining spacers on sidewalls of both the first and the second mandrels.

14. The method of claim 13 , further comprising:

selectively anisotropically etching the mandrels relative to the spacers to form a spacer pattern defined by the spacers; and

transferring the spacer pattern to the substrate.

15. The method of claim 14 , wherein the spacer pattern comprises elongated loops having connected ends, further comprising:

providing a mask over the loop ends;

transferring a pattern defined by the spacers to the substrate, wherein the mask blocks transfer of the loop ends to the substrate, wherein transferring the spacer pattern to the substrate defines unconnected lines derived from unblocked portions of the loops.

16. The method of claim 14 , wherein the spacer pattern comprises elongated loops having connected ends, further comprising removing the loop ends before transferring the spacer pattern to the substrate.

17. The method of claim 13 , wherein providing the tiered mandrel structure over the substrate comprises providing the tiered mandrel over a conductor.

18. The method of claim 13 , further comprising a third mandrel tier overlying the second mandrel tier, wherein the third mandrel tier has a third width less than the second width.

19. The method of claim 13 , wherein the masking layer is a photodefinable layer and wherein forming the pattern in the masking layer comprises performing photolithography.