Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
Spacers are formed by pitch multiplication and a layer of negative photoresist is deposited on and over the spacers to form additional mask features. The deposited negative photoresist layer is patterned, thereby removing photoresist from between the spacers in some areas. During patterning, it is not necessary to direct light to the areas where negative photoresist removal is desired, and the clean removal of the negative photoresist from between the spacers is facilitated. The pattern defined by the spacers and the patterned negative photoresist is transferred to one or more underlying masking layers before being transferred to a substrate.
1. A method for patterning a substrate, comprising:
providing an amorphous carbon layer over the substrate, and a photoresist layer over the amorphous carbon layer;
patterning the photoresist layer to form photoresist features;
blanket depositing a layer of spacer material over the photoresist features;
preferentially etching the spacer material from horizontal surfaces to define spacers on sidewalls of the photoresist features;
preferentially removing the photoresist features relative to the spacers;
transferring a pattern defined by the spacers to the amorphous carbon layer to define amorphous carbon mask features;
depositing negative photoresist over and between the amorphous carbon mask features;
patterning the negative photoresist to form a mask pattern defined by the amorphous carbon mask features and the negative resist; and
transferring the mask pattern to the substrate.
2. The method of claim 1 , further comprising trimming the photoresist features before said blanket depositing the layer of spacer material over the photoresist features.
3. The method of claim 2 , wherein said trimming the photoresist features before said blanket depositing the layer of spacer material over the photoresist features, comprises:
exposing the photoresist features to an isotropic etch.
4. The method of claim 1 , further comprising removing the spacers before said depositing the negative photoresist.
5. The method of claim 1 , wherein said blanket depositing the layer of spacer material over the photoresist features, comprises:
performing an atomic layer deposition to form the layer of spacer material.
6. The method of claim 1 , wherein the spacer material is silicon oxide.
7. The method of claim 1 , further comprising said transferring the pattern defined by the spacers to a hardmask layer before said transferring the pattern defined by the spacers to the amorphous carbon layer.
8. The method of claim 7 , wherein said providing the photoresist layer over the amorphous carbon layer comprises said providing the photoresist layer directly on the hardmask layer.
9. The method of claim 7 , wherein the hardmask layer comprises an antireflective coating.
10. The method of claim 1 , wherein the amorphous carbon is transparent carbon.
11. The method of claim 1 , wherein said transferring the mask pattern to the substrate defines interconnect lines.
12. The method of claim 1 , wherein said transferring the mask pattern to the substrate defines control gates of a memory device.
13. The method of claim 1 , wherein the spacers extend in spaced, generally parallel relation to one another for at least a part of a length of the spacers.
14. The method of claim 1 , wherein said patterning the negative photoresist to form the mask pattern defined by the amorphous carbon mask features and the negative resist, comprises:
forming non-pitch multiplied features.
15. The method of claim 14 , wherein said patterning the negative photoresist to form the mask pattern defined by the amorphous carbon mask features and the negative resist, comprises:
forming the non-pitch multiplied features in a periphery region of a partially-fabricated integrated circuit.
16. The method of claim 15 , wherein said patterning the negative photoresist to form the mask pattern defined by the amorphous carbon mask features and the negative resist, comprises:
exposing the amorphous carbon mask features in an array region of the partially-fabricated integrated circuit.