IP Library Granted Patent US 8,587,108
Granted Patent B2
US 8,587,108 · App. 13/188,069 · Granted Nov 19, 2013

Package for semiconductor device including guide rings and manufacturing method of the same

Inventors: HanShin Youn (Hwaseong-si, KR); Yonghwan Kwon (Suwon-si, KR); YoungHoon Ro (Hwaseong-si, KR); Woojae Kim (Hwaseong-si, KR); Sungwoo Park (Anyang-si, KR)
Assignee: Samsung Electronics Co., Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,587,108
App. No.
13/188,069
Granted
Nov 19, 2013
Kind
B2
Abstract

An example embodiment relates to a semiconductor package. The semiconductor package includes a first substrate including a first pad, a second substrate upwardly spaced apart from the first substrate and including a second pad opposite to the first pad. At least one electrode is coupled between the first pad and the second pad. The semiconductor package includes a guide ring formed at a periphery of the electrode between the first substrate and the second substrate.

Claims (63)

1. A semiconductor package comprising:

a first substrate including a first pad;

a second substrate upwardly spaced apart from the first substrate,

the second substrate including a second pad opposite to the first pad;

at least one electrode coupled between the first pad and the second pad; and

a guide ring formed at a periphery of the electrode between the first substrate and the second substrate,

wherein the guide ring includes a tube having uniform cross sections or a plurality of pillars and the at least one electrode is arranged inside the tube or inside the plurality of pillars.

2. The semiconductor package as set forth in claim 1 , wherein

the guide ring is configured to conform to a shape of the periphery of the at least one electrode.

3. The semiconductor package as set forth in claim 2 , wherein

the guide ring is arranged between the at least one electrode and an adjacent electrode, and

the guide ring is configured to prevent an electrical short between the at least one electrode and the adjacent electrode.

4. The semiconductor package as set forth in claim 2 , wherein

the guide ring includes a top surface and a bottom surface,

the top surface of the guide ring is connected to the second substrate, and

the bottom surface of the guide ring is connected to the first substrate.

5. The semiconductor package as set forth in claim 2 , wherein

the tube surrounds the at least one electrode,

and the tube is configured to conform to a circumference of the at least one electrode.

6. The semiconductor package as set forth in claim 5 , wherein

the at least one electrode includes at least one solder ball arranged within the guide ring.

7. The semiconductor package as set forth in claim 5 , wherein

the guide ring is arranged between the at least one electrode and an adjacent electrode, and

the guide ring is configured to prevent an electrical short between the at least one electrode and the adjacent electrode.

8. The semiconductor package as set forth in claim 2 , wherein

the electrode includes at least one solder ball arranged within the guide ring.

9. The semiconductor package as set forth in claim 2 , wherein

the guide ring is arranged between the at least one electrode and an adjacent electrode, and

the guide ring is configured to prevent an electrical short between the at least one electrode and the adjacent electrode.

10. The semiconductor package as set forth in claim 1 , wherein

the plurality of pillars include at least four pillars, each pillar is positioned at a different position along the circumference of the at least one electrode such that a line between each adjacent pillar forms a four-sided perimeter surrounding the at least one electrode.

11. The semiconductor package as set forth in claim 10 , wherein

the guide ring includes a top surface and a bottom surface,

the top surface of the guide ring is connected to the second substrate, and

the bottom surface of the guide ring is connected to the first substrate.

12. The semiconductor package as set forth in claim 1 , wherein

the guide ring contains one of a dielectric material and a high-molecular compound.

13. The semiconductor package as set forth in claim 12 , wherein

the first substrate further includes a first photo solder resist configured to support the guide ring, and

the second substrate further includes a second photo solder resist supported by the guide ring.

14. A semiconductor package comprising:

a first substrate including a first pad;

a second substrate upwardly spaced apart from the first substrate and including a second pad opposite to the first pad;

at least one electrode coupled between the first pad and the second pad;

a guide ring formed at a periphery of the at least one electrode between the first substrate and the second substrate,

the guide ring including a top surface and a bottom surface, the top surface of the guide ring is connected to the second substrate, and the bottom surface of the guide ring is connected to the first substrate,

wherein the guide ring includes a tube having uniform cross sections or a plurality of pillars and the at least one electrode is arranged inside the tube or inside the plurality of pillars.

15. The semiconductor package as set forth in claim 14 , wherein

the plurality of pillars include at least four pillars, each pillar is positioned at a different position along the circumference of the electrode such that a line between each adjacent pillar forms a four-sided perimeter surrounding the at least one electrode.

16. A semiconductor package comprising:

a first substrate including a first pad;

a second substrate upwardly spaced apart from the first substrate,

the second substrate including a second pad opposite to the first pad;

at least one electrode coupled between the first pad and the second pad; and

a guide ring formed at a periphery of the at least one electrode between the first substrate and the second substrate,

wherein the first substrate further includes a first photo solder resist configured to support the guide ring, and

the second substrate further includes a second photo solder resist supported by the guide ring.

17. The semiconductor package as set forth in claim 16 , wherein

the guide ring is on the first photo solder resist at a circumference of the first pad.

18. The semiconductor package as set form in claim 1 , wherein

the guide ring is configured to conform to a circumference of the at least one electrode.

19. The semiconductor package as set form in claim 14 , wherein

the guide ring is configured to conform to a circumference of the at least one electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 2, 2011
From: YOUN, HANSHIN; KWON, YONGHWAN; RO, YOUNGHOON; KIM, WOOJAE; PARK, SUNGWOO
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 026856/0324 →
Priority Claims (1)
KR 10-2010-0094617 · Sep 29, 2010 · national
Continuity (1)
Related Publication 20120074566A1 · Mar 29, 2012