Leakage measurement systems
Described examples include leakage measurement systems and methods for measuring leakage current between a word line at a boosted voltage and a word line at a supply voltage. The boosted voltage may be generated by charge pump circuitry. Examples of leakage measurement systems described herein may be included in memory devices.
1. A memory device, comprising:
a plurality of memory cells;
a plurality of word lines coupled to the plurality of memory cells;
charge pump circuitry configured to generate a boosted voltage from a supply voltage; and
a leakage measurement system coupled to the plurality of word lines, the leakage measurement circuit configured to provide the boosted voltage to at least a first one of the plurality of word lines and the supply voltage to at least a second one of the plurality of word lines, wherein the leakage measurement circuit is further configured to generate a reference current, provide the reference current to the second one of the plurality of word lines, and determine whether leakage current received at the second one of the plurality of word lines is acceptable relative to the reference current.
2. The memory device of claim 1 , wherein the leakage measurement system comprises:
a current generation circuit configured to generate the reference current;
a comparator having a first input coupled to the second one of the plurality of word lines and a second input configured to receive the supply voltage, wherein the comparator is configured to generate a signal indicative of a comparison between the supply voltage and a voltage on the second one of the plurality of word lines.
3. The memory device of claim 2 , further comprising:
logic coupled to the comparator and configured to generate a signal indicating whether the leakage current on the one of the plurality of word lines is acceptable.
4. The memory device of claim 1 , further comprising:
a row decoder coupled to the charge pump circuitry and the leakage measurement system, wherein the row decoder is configured to provide the boosted voltage to the first one of the plurality of word lines.
5. The memory device of claim 1 , wherein the leakage measurement system comprises a plurality of measurement enable circuits and a plurality of comparators, and wherein:
individual ones of the plurality of measurement enable circuits are coupled to a respective one of the plurality of word lines and a respective one of the plurality of comparators;
individual ones of the plurality of measurement enable circuits are configured to provide the boosted voltage to the respective one of the plurality of word lines responsive to a first control signal;
individual ones of the plurality of measurement enable circuits further configured to decouple the respective one of the plurality of word lines from the boosted voltage responsive to a second control signal, and
individual ones of the plurality of measurement enable circuits further configured to supply the reference current to the respective one of the plurality of word lines by coupling the respective one of the plurality of word lines to a current generation circuit responsive to the second control signal.
6. The memory device of claim 5 , further comprising:
logic coupled to the plurality of comparators and configured to generate a signal indicating whether the leakage current on the one of the plurality of word lines is acceptable.
7. The memory device of claim 6 , wherein the logic comprises an AND gate.
8. A leakage measurement system comprising:
measurement enable circuitry configured to precharge a first word line to a first voltage;
charge pump circuitry configured to generate a second voltage, wherein the second voltage is higher than the first voltage, and provide the second voltage to at least a second word line; and
a current source configured to provide a reference current to the first word line; wherein a voltage on the first word line is based, at least in part, on a magnitude of a leakage current between the first and second word lines relative to the reference current.
9. The leakage measurement system of claim 8 , further comprising:
a comparator coupled to the first word line, wherein the comparator is configured to compare the voltage on the first word line with the first voltage and generate a signal indicative of the comparison.
10. The leakage measurement system of claim 8 , wherein the measurement enable circuitry is further configured to precharge a third word line to the first voltage, and wherein the charge pump circuitry is further configured to provide the second voltage to at least a fourth word line, and wherein a voltage on the third word line is based, at least in part, on a magnitude of a leakage current between the third and fourth word lines relative to the reference current.
11. The leakage measurement system of claim 10 , wherein the current source is a first current source, the leakage measurements system further comprising a second current source configured to provide the reference current to the third word line.
12. The leakage measurement system of claim 10 , further comprising:
a first comparator coupled to the first word line, wherein the first comparator is configured to compare the voltage on the first word line with the first voltage and generate a first signal indicative of the comparison;
a second comparator coupled to the third word line, wherein the second comparator is configured to compare the voltage on the third word line with the first voltage and generate a second signal indicative of the comparison; and
logic coupled to the first and second comparators and configured to generate a fail signal if either of the first or second signals indicates unacceptable leakage current.
13. The leakage measurement system of claim 12 , wherein the logic comprises an AND gate.
14. The leakage measurement system of claim 10 , wherein the voltage on the first word line is based, at least in part, on leakage currents between the first word line and both the second and fourth word lines.
15. A method comprising:
charging a first word line of a memory device to a supply voltage;
charging a second word line of the memory device to a boosted voltage, greater than the supply voltage; and
generating a signal, using a system in the memory device, wherein the signal is based, at least in part, on a leakage current between the first word line and the second word line.
16. The method of claim 15 , further comprising generating the boosted voltage using charge pump circuitry of the memory device.
17. The method of claim 15 , further comprising providing a reference current to the first word line, and wherein a voltage on the first word line is based, at least in part on the leakage current between the first word line and the second word line.
18. The method of claim 17 , further comprising comparing the voltage on the first word line with the supply voltage to generate the signal.
19. The method of claim 15 , wherein the signal is a first signal, the method further comprising:
charging a third word line of the memory device to the supply voltage;
charging a fourth word line of the memory device to the boosted voltage;
generating a second signal, using the system in the memory device, wherein the second signal is based, at least in part, on a leakage current between the third word line and the fourth word line.
20. The method of claim 19 , further comprising combining the first and second signals to generate a pass signal or a fail signal indicating whether the memory device has acceptable or unacceptable leakage current.
21. The method of claim 19 , wherein the first signal is based, at least in part, on leakage current between the first word line and the second and fourth word lines.