IP Library Granted Patent US 8,592,319
Granted Patent B2
US 8,592,319 · App. 13/167,574 · Granted Nov 26, 2013

Substrate processing method and substrate processing apparatus

Inventors: Nobuhiro Wada (Nirasaki, JP); Makoto Kobayashi (Hsinchu, TW); Hiroshi Tsujimoto (Nirasaki, JP); Jun Tamura (Nirasaki, JP); Mamoru Naoi (Nirasaki, JP); Jun Oyabu (Nirasaki, JP)
Assignee: Tokyo Electron Limited
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Quick Facts
Patent No.
US 8,592,319
App. No.
13/167,574
Granted
Nov 26, 2013
Kind
B2
Abstract

A substrate processing apparatus includes a chamber accommodating a wafer, a susceptor disposed inside the chamber and on which the wafer is held, an upper electrode facing the susceptor, and a second high frequency power source connected to the susceptor, wherein the upper electrode is electrically connected to a ground and is moveable with respect to the susceptor. The substrate processing apparatus divides a potential difference between plasma generated in a processing space and the ground into a potential difference between the plasma and a dielectric and a potential difference between the dielectric and the ground by burying the dielectric in the upper electrode, and changes a gap between the upper electrode and the susceptor. Accordingly, plasma density between the upper electrode and the susceptor is changed.

Claims (11)

1. A substrate processing method for performing an etching process on a substrate by using plasma in a substrate processing apparatus, the substrate processing apparatus comprising an accommodating chamber which accommodates the substrate, a lower electrode which is disposed inside the accommodating chamber and on which the substrate is held, an upper electrode which faces the lower electrode, a high frequency power source which is connected to the lower electrode, a processing space between the upper electrode and the lower electrode, and a ground which is electrically connected to the upper electrode, one of the upper electrode and the lower electrode being moveable with respect to the other, and the substrate processing method comprising:

dividing a potential difference between plasma generated in the processing space and the ground into a potential difference between the plasma and a dielectric and a potential difference between the dielectric and the ground, by the dielectric buried in at least a portion of the upper electrode;

performing a first process on the substrate while an interval between the upper electrode and the lower electrode is maintained to a first distance;

changing an etching rate by changing the interval to a second distance after the first process; and

performing a second process on the substrate by using the changed etching rate while maintain the interval to the second distance.

2. The substrate processing method of claim 1 , wherein the upper electrode is an electrode having a plate shape, and the dielectric is provided along a plane direction of the upper electrode.

3. The substrate processing method of claim 2 , wherein the dielectric is provided only in a portion, of the upper electrode, facing a central portion of the substrate held on the lower electrode.

4. The substrate processing method of claim 2 , wherein the dielectric has a circular plate shape having a through hole in a central portion of the dielectric, and is buried in the upper electrode such that the through hole faces a central portion of the substrate held on the lower electrode.

5. The substrate processing method of claim 1 , wherein the interval between the upper electrode and the lower electrode is decreased, thereby increasing the etching rate.

6. The substrate processing method of claim 1 , wherein the dielectric is formed of any one of quartz, yttria (Y 2 O 3 ), alumina (Al 2 O 3 ), silica (SiO 2 ), aluminum nitride (AlN), boron nitride (BN), and silicon carbide (SiC).

7. The substrate processing method of claim 1 , wherein a thickness of the dielectric is equal to or larger than 10 mm and equal to or smaller than 15 mm.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2011
From: WADA, NOBUHIRO; KOBAYASHI, MAKOTO; TSUJIMOTO, HIROSHI; TAMURA, JUN; NAOI, MAMORU; OYABU, JUN
To: TOKYO ELECTRON LIMITED
Reel/Frame 026762/0852 →
Priority Claims (1)
JP 2010-144164 · Jun 24, 2010 · national
Continuity (2)
Provisional Application 61362465 · Jul 8, 2010
Related Publication 20110318934A1 · Dec 29, 2011