IP Library Granted Patent US 8,592,957
Granted Patent B2
US 8,592,957 · App. 13/390,184 · Granted Nov 26, 2013

Semiconductor device having shield layer and chip-side power supply terminal capacitively coupled therein

Inventor: Yoshiaki Wakabayashi (Tokyo, JP)
Assignee: NEC Corporation
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Quick Facts
Patent No.
US 8,592,957
App. No.
13/390,184
Granted
Nov 26, 2013
Kind
B2
Abstract

Provided is a semiconductor device including a wiring board having a first surface on which a board-side ground terminal and a board-side power supply terminal are provided; a semiconductor chip arranged so as to face the first surface of the wiring board, where the first surface faces an opposite surface of the semiconductor chip; a shield layer provided at the semiconductor chip so as to cover an outer surface of the semiconductor chip except for the opposite surface; a chip-side power supply terminal which is provided on the opposite surface and is electrically connected to the board-side power supply terminal; a chip-side ground terminal which is provided on the opposite surface and is electrically connected to the board-side ground terminal and the shield layer; and a first capacitively coupled part by which the shield layer and the chip-side power supply terminal are capacitively coupled with each other.

Claims (20)

1. A semiconductor device comprising:

a wiring board comprising a first surface on which a board-side ground terminal and a board-side power supply terminal are provided;

a semiconductor chip arranged so as to face the first surface of the wiring board, where the first surface faces an opposite surface of the semiconductor chip;

a shield layer provided at the semiconductor chip so as to cover an outer surface of the semiconductor chip except for the opposite surface;

a chip-side power supply terminal which is provided on the opposite surface and is electrically connected to the board-side power supply terminal;

a chip-side ground terminal which is provided on the opposite surface and is electrically connected to the board-side ground terminal and the shield layer; and

a first capacitively coupled part by which the shield layer and the chip-side power supply terminal are capacitively coupled with each other, and

wherein the first capacitively coupled part comprises inter-digital electrodes which are respectively formed at the shield layer and the chip-side power supply terminal, the inter-digital electrodes each having a comb shape, and are separated from and engaged with each other.

2. The semiconductor device in accordance with claim 1 , wherein the semiconductor chip is connected to the wiring board by using a flip-chip connection.

3. The semiconductor device in accordance with claim 1 , further comprising:

an electronic circuit provided on the opposite surface,

wherein a plurality of the chip-side power supply terminals are provided around the electronic circuit.

4. The semiconductor device in accordance with claim 1 , further comprising:

a second capacitively coupled part by which at least one chip-side power supply terminal and the chip-side ground terminal are capacitively coupled with each other.

5. The semiconductor device in accordance with claim 4 , wherein the second capacitively coupled part comprises inter-digital electrodes which are respectively formed at the chip-side power supply terminal and the chip-side ground terminal, where the inter-digital electrodes each have a comb shape, and are separated from and engaged with each other.

6. The semiconductor device in accordance with claim 1 , further comprising:

a third capacitively coupled part by which at least one pair of the chip-side power supply terminals adjacent to each other are capacitively coupled with each other.

7. The semiconductor device in accordance with claim 6 , wherein the third capacitively coupled part comprises inter-digital electrodes which are respectively formed at the adjacent chip-side power supply terminals, where the inter-digital electrodes each have a comb shape, and are separated from and engaged with each other.

8. The semiconductor device in accordance with claim 1 , wherein the first capacitively coupled part is formed by connecting the shield layer and the chip-side power supply terminal via a dielectric, and comprises a capacitive element comprising a Metal-Insulator-Metal Capacitor (MIMC) structure.

9. The semiconductor device in accordance with claim 1 , wherein the shield layer and the chip-side ground terminal are directly and electrically connected via a conductor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2012
From: WAKABAYASHI, YOSHIHAKI
To: NEC CORPORATION
Reel/Frame 027824/0304 →
Priority Claims (1)
JP P2009-189130 · Aug 18, 2009 · national
Continuity (1)
Related Publication 20120139091A1 · Jun 7, 2012