Semiconductor device
A normally off semiconductor device with a reduced off-state leakage current, which is applicable to a power switching element, includes: a substrate; an undoped GaN layer formed above the substrate; an undoped AlGaN layer formed on the undoped GaN layer; a source electrode and a drain electrode, formed on the undoped GaN layer or the undoped AlGaN layer; a P-type GaN layer formed on the undoped AlGaN layer and disposed between the source electrode and the drain electrode; and a gate electrode formed on the P-type GaN layer, wherein the undoped GaN layer includes an active region including a channel and an inactive region not including the channel, and the P-type GaN layer is disposed to surround the source electrode.
1. A semiconductor device comprising:
a substrate;
a first nitride semiconductor layer formed above said substrate;
a second nitride semiconductor layer formed on said first nitride semiconductor layer and having a higher bandgap energy than said first nitride semiconductor layer;
a source electrode and a drain electrode which are formed on one of said first nitride semiconductor layer and said second nitride semiconductor layer;
a third nitride semiconductor layer of P-type conductivity formed on said second nitride semiconductor layer and disposed between said source electrode and said drain electrode; and
a gate electrode formed on said third nitride semiconductor layer,
wherein said first nitride semiconductor layer includes an active region and an inactive region, the active region including a channel, and the inactive region not including the channel, and
said third nitride semiconductor layer is disposed to surround at least one of said source electrode and said drain electrode.
2. The semiconductor device according to claim 1 ,
wherein the inactive region is formed by ion implantation of non-conducting impurities.
3. The semiconductor device according to claim 1 ,
wherein said third nitride semiconductor layer is disposed so as to cross an interface between the inactive region and the active region.
4. The semiconductor device according to claim 1 ,
wherein said third nitride semiconductor layer is disposed so as not to cross an interface between the inactive region and the active region.
5. The semiconductor device according to claim 1 ,
wherein said gate electrode is disposed to surround one of said source electrode and said drain electrode.
6. The semiconductor device according to claim 1 ,
wherein a recess is formed in said second nitride semiconductor layer, and
said third nitride semiconductor layer is formed in the recess.
7. The semiconductor device according to claim 1 , further comprising
an insulating film formed between said third nitride semiconductor layer and said gate electrode.
8. The semiconductor device according to claim 1 ,
wherein said first nitride semiconductor layer includes Al x Ga 1−x N (0≦x≦1),
said second nitride semiconductor layer includes Al y Ga 1−y N (0<y≦1), and
said third nitride semiconductor layer includes Al z Ga 1−z N (0≦z≦1).
9. The semiconductor device according to claim 1 , which is a normally off transistor.
10. The semiconductor device according to claim 1 ,
wherein two third nitride semiconductor layers each of which is said third nitride semiconductor layer are provided between said source electrode and said drain electrode,
one of said two third nitride semiconductor layers is disposed to surround said source electrode, and the other of said two third nitride semiconductor layers is disposed to surround said drain electrode,
two gate electrodes each of which is said gate electrode are provided, and
a first gate electrode that is one of said two gate electrodes is formed on said third nitride semiconductor layer which surrounds said source electrode, and a second gate electrode that is the other of said two gate electrodes is formed on said third nitride semiconductor layer which surrounds said drain electrode.
11. The semiconductor device according to claim 10 ,
wherein said third nitride semiconductor layer is disposed so as to cross an interface between the inactive region and the active region.
12. The semiconductor device according to claim 10 ,
wherein said gate electrode is disposed to surround one of said source electrode and said drain electrode.
13. The semiconductor device according to claim 10 ,
wherein a recess is formed in said second nitride semiconductor layer, and
said third nitride semiconductor layer is formed in the recess.
14. The semiconductor device according to claim 10 , further comprising
an insulating film formed between said third nitride semiconductor layer and said gate electrode.
15. The semiconductor device according to claim 10 ,
wherein said first nitride semiconductor layer includes Al x Ga 1−x N (0≦x≦1),
said second nitride semiconductor layer includes Al y Ga 1−y N (0<y≦1), and
said third nitride semiconductor layer includes Al z Ga 1−z N (0≦z≦1).
16. The semiconductor device according to claim 10 , which is a normally off transistor.