High electron mobility transistor structure with improved breakdown voltage performance
A HEMT includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate, a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer, and a passivation material layer having one or more buried portions contacting or almost contacting the UID GaN layer. A carrier channel layer at the interface of the donor-supply layer and the UID GaN layer has patches of non-conduction in a drift region between the gate and the drain. A method for making the HEMT is also provided.
1. A high electron mobility transistor (HEMT) comprising:
a silicon substrate;
an unintentionally doped gallium nitride (UID GaN) layer over the substrate;
a donor-supply layer over the UID GaN layer;
a carrier channel layer at an interface of the UID GaN layer and the donor-supply layer;
a gate structure, a drain, and a source over the donor-supply layer, said gate structure disposed between the drain and the source;
a passivation layer over the donor-supply layer between the gate structure and the drain, the passivation layer having a dielectric constant less than that of the donor-supply layer;
wherein the carrier channel layer has a smaller surface area than the UID GaN layer in a drift region between the gate structure and the drain.
2. The HEMT of claim 1 , wherein a minimum width of the carrier channel layer is 50% or greater than the width of the UID GaN layer.
3. The HEMT of claim 1 , wherein the donor-supply layer is discontinuous in the drift region.
4. The HEMT of claim 3 , wherein the passivation layer has one or more first portions contacting the UID GaN layer through one or more discontinuities in the donor-supply layer and a second portion over the first portion and the donor-supply layer.
5. The HEMT of claim 4 , wherein the one or more first portions of the passivation layer are quadrilaterals in a top view.
6. The HEMT of claim 5 , wherein none of the one or more first portions of the passivation layer adjoins the gate.
7. The HEMT of claim 1 , wherein one or more portions of the donor-supply layer in the drift region have a thickness about or less than 3 nanometer.
8. The HEMT of claim 5 , wherein the passivation layer has one or more first portions in the donor-supply layer and a second portion over the first portion and the donor-supply layer.
9. The HEMT of claim 1 , wherein the passivation layer comprises silicon oxide, silicon nitride, silicon oxynitride, carbon doped silicon oxide, carbon doped silicon nitride, or carbon doped silicon oxynitride.
10. The HEMT of claim 1 further comprising a buried oxide layer adjoining a gate edge, said buried oxide layer being surrounded by the donor-supply layer.
11. The HEMT of claim 1 , further comprising a field plate over the gate structure.
12. The HEMT of claim 1 , wherein the donor-supply layer comprises undoped aluminum nitride or undoped aluminum gallium nitride.
13. A high electron mobility transistor (HEMT) comprising:
a silicon substrate;
an unintentionally doped gallium nitride (UID GaN) layer over the substrate;
a donor-supply layer over the UID GaN layer;
a carrier channel layer at an interface of the UID GaN layer and the donor-supply layer;
a gate structure, a drain, and a source over the donor-supply layer, said gate structure disposed between the drain and the source, wherein the donor-supply layer has one or more through-holes in a drift region between the gate structure and the drain; and,
a passivation layer over the donor-supply layer and filling the one or more through-holes.
14. The HEMT of claim 13 , wherein a minimum width of the carrier channel layer is about 50% to about 90% of the width of the UID GaN layer.
15. The HEMT of claim 13 , wherein the passivation layer has a dielectric constant less than about 9.
16. A high electron mobility transistor (HEMT) comprising:
a silicon substrate;
an unintentionally doped gallium nitride (UID GaN) layer over the substrate;
a donor-supply layer over the UID GaN layer;
a carrier channel layer at an interface of the UID GaN layer and the donor-supply layer;
a gate structure, a drain, and a source over the donor-supply layer, said gate structure disposed between the drain and the source, wherein the donor-supply layer has a plurality of through-holes;
a passivation layer over the donor-supply layer between the gate structure and the drain, the passivation layer having a dielectric constant less than that of the donor-supply layer and filling the plurality of through-holes;
wherein the carrier channel layer has a smaller surface area than the UID GaN layer in a drift region between the gate structure and the drain.
17. The high electron mobility transistor (HEMT) of claim 16 , wherein a minimum width of the carrier channel layer is 50% or greater than the width of the UID GaN layer.
18. The HEMT of claim 16 , wherein the donor-supply layer is discontinuous in the drift region.
19. The HEMT of claim 18 , wherein the passivation layer has one or more first portions contacting the UID GaN layer through one or more discontinuities in the donor-supply layer and a second portion over the first portion and the donor-supply layer.
20. The HEMT of claim 19 , wherein the one or more first portions of the passivation layer are quadrilaterals in a top view.