Method for manufacturing trench type superjunction device and trench type superjunction device
A method for manufacturing trench type super junction device is disclosed. The method includes the step of forming one or more P type implantation regions in the N type epitaxial layer below the bottom of each trench. By using this method, a super junction device having alternating P type and N type regions is produced, wherein the P type region is formed by P type silicon filled in the trench and P type implantation regions below the trench. The present invention can greatly improve the breakdown voltage of a super junction MOSFET.
1. A method for manufacturing trench type super junction device, comprising the following steps:
depositing a dielectric film on a first type epitaxial layer and forming one or more trenches in the first type epitaxial layer by photolithograph and etch, wherein the first type epitaxial layer is formed on a substrate;
forming one or ore second type implantation regions below each trench by ion implantation;
filling the trenches with a second type semiconductor layer; and
removing the second type semiconductor layer and the dielectric film above the first type epitaxial layer by chemical mechanical polishing and/or etch back process;
wherein the first type is N type while the second type is P type, or the first type is P type while the second type is N type.
2. The method as claimed in claim 1 , wherein:
the one or more second type implantation regions are formed between the bottom of each trench and the substrate;
the second type implantation region may connect or disconnect with the bottom of the trench;
the second type implantation region may connect or disconnect with the substrate.
3. The method as claimed in claim 1 , wherein the second type semiconductor layer is made of a second type silicon layer, or made of a second type silicon layer and a non-doped silicon layer formed in sequence, or made of a second type silicon layer and a dielectric layer formed in sequence.
4. The method as claimed in claim 1 , wherein the trenches may have a vertical profile or an oblique profile; the trenches may have a flat bottom shape or a curved bottom shape.
5. The method as claimed in claim 1 , wherein the dielectric film is a silicon oxide film formed by thermal oxidation or chemical vapor deposition process.
6. A trench type super junction device, formed by using the method as claimed in claim 1 , wherein the device comprises alternating first type and second type thin layers, the first type thin layer being formed by the first type epitaxial layer, the second type thin layer being formed by the second type semiconductor layer filled in the trench and the one or more second type implantation regions below the corresponding trench.
7. The method as claimed in claim 2 , wherein a single step of ion implantation by using second type impurities is performed to form a second type implantation region below each trench.
8. The method as claimed in claim 2 , wherein multiple steps of ion implantation by using second type impurities are performed to form more than one second type implantation regions below each trench.
9. The method as claimed in claim 2 , wherein a total quantity of second type impurities in the second type semiconductor layer and the second type implantation regions is equal with a total quantity of first type impurities in the first type epitaxial layer.
10. The method as claimed in claim 2 , wherein the second type implantation regions have an impurity concentration of the same order of magnitude with an impurity concentration of the second type semiconductor layer.
11. A trench type super junction device, formed by using the method as claimed in claim 2 , wherein the device comprises alternating first type and second type thin layers, the first type thin layer being formed by the first type epitaxial layer, the second type thin layer being formed by the second type semiconductor layer filled in the trench and the one or more second type implantation regions below the corresponding trench.
12. The method as claimed in claim 3 , wherein the second type silicon layer is made of monocrystal silicon, polycrystal silicon or amorphous silicon, the second type silicon layer being formed under a temperature of 650˜1200 degrees.
13. The method as claimed in claim 3 , wherein the non-doped silicon layer is formed under a temperature of 510˜650 degrees.
14. The method as claimed in claim 3 , wherein the dielectric layer is non-doped silicon oxide or BPSG.
15. The method as claimed in claim 7 , wherein the single step of ion implantation has an implant energy of 0.5 Kev˜1000 Kev, an implant dose of 1E11˜1E14/cm 2 , and an implant angle of 0˜10 degrees.
16. The method as claimed in claim 8 , wherein the multiple steps of ion implantation use different implant energies to form more than one second type implantation regions along a vertical direction, the second type implantation regions being connected to one another or being separate from one another.
17. The method as claimed in claim 8 , wherein:
the implant energies of the multiple steps of ion implantation range from 0.5 Kev to 1000 Kev;
the step of ion implantation with the highest implant energy is performed first and the step of ion implantation with the lowest implant energy is performed last, or the step of ion implantation with the lowest implant energy is performed first and the step of ion implantation with the highest implant energy is performed last.
18. The method as claimed in claim 8 , wherein the multiple steps of ion implantation have an implant dose of 1E11˜1E14/cm 2 , and an implant angle of 0˜10 degrees.