Etching high K dielectrics with high selectivity to oxide containing layers at elevated temperatures with BC13 based etch chemistries
Wafers having a high K dielectric layer and an oxide or nitride containing layer are etched in an inductively coupled plasma processing chamber by applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl 3 , setting the temperature of the wafer to be between 100° C. and 350° C., and etching the wafer with a selectivity of high K dielectric to oxide or nitride greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a reactive ion etch processing chamber by applying a bias power to the wafer, introducing into the chamber a gas including BCl 3 , setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a an inductively coupled plasma processing chamber by applying a bias power to the wafer, applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl 3 , setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1.
1. A method for etching a high K dielectric layer during fabrication of a semiconductor device comprising:
providing a wafer into a plasma etch processing chamber, wherein said wafer comprises the high K dielectric layer and a silicon oxide containing layer;
applying a source power of between about 200 watts and 600 watts to generate an inductively coupled plasma;
introducing into said plasma etch processing chamber a gas consisting essentially of BCl 3 and CH 4 ;
heating said wafer to a temperature of between about 175° C. and 225° C.;
controlling a process pressure in the plasma etch processing chamber at between about 4 mTorr and 50 mTorr; and
while applying the source power, heating the wafer, and controlling the process pressure, etching the high K dielectric layer with a selectivity of the high K dielectric layer to the silicon oxide containing layer of greater than 10:1.
2. The method of claim 1 wherein said high K dielectric layer comprises one of HfO 2 and Al 2 O 3 .
3. The method of claim 1 wherein said high K dielectric layer is located over said silicon oxide containing layer and wherein said etching step is stopped before a substantial amount of said silicon oxide containing layer is etched.
4. The method of claim 1 further comprising applying a bias power to said wafer.
5. The method of claim 4 wherein said bias power is less than 100 watts.
6. A method for etching a high K dielectric layer during fabrication of a semiconductor device comprising:
providing a wafer into a plasma etch processing chamber, wherein said wafer comprises the high K dielectric layer and a silicon oxide containing layer;
applying a source power to generate an inductively coupled plasma;
introducing into said plasma etch processing chamber a gas consisting essentially of BCl 3 and CH 4 ;
heating said wafer to a temperature of between about 175° C. and 225° C.; and
while applying the source power and heating the wafer, etching the high K dielectric layer with a selectivity of the high K dielectric layer to the silicon oxide containing layer of greater than 10:1.
7. The method of claim 6 wherein said high K dielectric layer comprises one of HfO 2 and Al 2 O 3 .
8. The method of claim 6 wherein said high K dielectric layer is located over said silicon oxide containing layer and wherein said etching step is stopped before a substantial amount of said silicon oxide containing layer is etched.
9. A method for etching a high K dielectric layer during fabrication of a semiconductor device comprising:
providing a wafer into a plasma etch processing chamber, wherein said wafer comprises the high K dielectric layer and a silicon oxide containing layer;
applying a source power of between about 200 watts and 600 watts to generate an inductively coupled plasma;
introducing into said plasma etch processing chamber a gas consisting essentially of BCl 3 and CH 4 ;
heating said wafer to a temperature of between about 100° C. and 350° C.;
controlling a process pressure in the plasma etch processing chamber at between about 4 mTorr and 50 mTorr; and
while applying the source power, heating the wafer, and controlling the process pressure, etching the high K dielectric layer with a selectivity of the high K dielectric layer to the silicon oxide containing layer of greater than 10:1.
10. The method of claim 9 wherein said high K dielectric layer comprises one of HfO 2 and Al 2 O 3 .
11. The method of claim 9 wherein said high K dielectric layer is located over said silicon oxide containing layer and wherein said etching step is stopped before a substantial amount of said silicon oxide containing layer is etched.