Copper etch scheme for copper interconnect structure
The present disclosure is directed to a method of manufacturing an interconnect structure in which a low-k dielectric layer is formed over a semiconductor substrate followed by formation of a copper or copper alloy layer over the low-k dielectric layer. The copper or copper alloy layer is patterned and etched to form a copper body having recesses, which are then filled with a low-k dielectric material. The method allows for formation of a damascene structures without encountering the various problems presented by non-planar features and by porus low-K dielectric damage.
1. A method for forming an interconnect structure, comprising:
providing a semiconductor substrate having a conductive region at a surface of the substrate;
forming a layer of a low-k dielectric material over the substrate and covering the conductive region;
depositing a metal layer of copper or copper alloy overlying the dielectric layer;
forming a barrier layer between the low-k dielectric material and the copper or copper alloy metal layer;
patterning and etching the copper or copper alloy metal layer to define a first feature having a copper or copper alloy body with first recesses about opposing sidewalls of the body;
patterning and etching the copper or copper alloy body to define a second feature having second recesses in an upper portion of the body to define a via,
wherein the metal layer is copper and forming the barrier layer comprises forming a first barrier layer overlying the low-k dielectric and subsequently forming a second barrier layer overlying the via.
2. The method of claim 1 , wherein the first barrier layer and second barrier layer are continuous.
3. The method of claim 2 , wherein the first and second barrier layers comprise the same material or different materials.
4. A method for forming a copper interconnect structure, comprising:
providing a semiconductor substrate;
forming a low k dielectric layer overlying the semiconductor substrate;
forming a single, continuous metal layer of copper or copper alloy over the low-k dielectric;
removing a portion of the single, continuous metal layer of copper or copper alloy to form a single, continuous copper or copper alloy body with first recesses about opposing sidewalls thereof;
patterning the single, continuous copper or copper alloy body to form second recesses in an upper region of the single, continuous copper or copper alloy body to define a vertical element extending upward from a lower region of the single, continuous copper or copper alloy body;
depositing low-k dielectric to fill first and second recesses and overlying an upper surface of the vertical element; and
performing a chemical mechanical polishing to expose a top surface of the upper region of the single, continuous copper or copper alloy body.
5. The method of claim 4 , wherein forming first recesses exposes an upper surface of the low-k dielectric layer.
6. The method of claim 5 , wherein second recesses extend approximately one-half the thickness of the body.
7. The method of claim 4 , wherein the upper region of the body is a via and the lower region of the body is an interconnect line.
8. The method of claim 4 , further comprising forming an additional copper or copper alloy layer overlying the via and electrically coupled to the via.
9. A method for forming a copper interconnect structure, comprising:
providing a semiconductor substrate;
forming a low k dielectric layer overlying the semiconductor substrate;
forming a metal layer of copper or copper alloy over the low-k dielectric;
removing a portion of the copper or copper alloy layer to form a copper or copper alloy body with first recesses about opposing sidewalls of the copper or copper alloy body;
patterning and etching the copper or copper alloy body to form second recesses in an upper region of the body to define a vertical element extending upward from a lower region of the body; and
depositing low-k dielectric to fill first and second recesses and overlying a top surface of the vertical element of the copper or copper alloy body,
wherein after the low-k dielectric has been deposited to fill recesses, performing an anneal to form a barrier layer between the copper or copper alloy body and the low-k dielectric.
10. The method of claim 9 , and further comprising:
subsequent to depositing the low-k dielectric to fill recesses, performing a planarization process to expose the top surface of the upper region of the copper or copper alloy body;
forming an additional metal layer of copper or copper alloy over the exposed top surface of the upper region of the copper or copper alloy body;
patterning the additional metal layer to form a metal feature of copper or copper alloy over the top surface of the upper region of the copper or copper alloy body;
depositing another low-k dielectric over the patterned metal feature of copper or copper alloy; and
performing an anneal to form another barrier layer between the patterned metal feature of copper or copper allow and the another low-k dielectric.
11. A method for forming a copper interconnect structure, comprising:
providing a semiconductor substrate;
forming a low k dielectric layer overlying the semiconductor substrate;
forming a single, continuous metal layer of copper or copper alloy over the low-k dielectric;
removing a portion of the single, continuous metal layer of copper or copper alloy to form a single, continuous copper or copper alloy body with first recesses about opposing sidewalls thereof;
patterning the single, continuous copper or copper alloy body to form second recesses in an upper region of the single, continuous copper or copper alloy body to define a vertical element extending upward from a lower region of the single, continuous copper or copper alloy body;
depositing low-k dielectric to fill first and second recesses and overlying an upper surface of the vertical element; and
forming a barrier layer over a top and sides of the vertical element extending upward from the lower region of the single, continuous copper or copper alloy body prior to depositing the low-k dielectric to fill the first and second recesses. dielectric to fill the first and second recesses.