Determining soft data for combinations of memory cells
The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells including a first and a second memory cell each programmable to one of a number of program states, wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states, and a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program states of the first and second memory cells.
1. An apparatus, comprising
an array of memory cells, wherein:
the array includes a first memory cell and a second memory cell, wherein the first and second memory cells are each programmable to one of a number of program states; and
a combination of the program states of the first and second memory cells corresponds to one of a number of data states; and
a buffer and/or a controller coupled to the array and configured to:
determine soft data associated with the program states of the first and second memory cells; and
determine soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program state of the first memory cell and the soft data associated with the program state of the second memory cell.
2. The apparatus of claim 1 , wherein:
the soft data associated with the program state of the first memory cell indicates a location of a threshold voltage associated with the first memory cell within a threshold voltage distribution associated with the program state of the first memory cell; and
the soft data associated with the program state of the second memory cell indicates a location of a threshold voltage associated with the second memory cell within a threshold voltage distribution associated with the program state of the second memory cell.
3. The apparatus of claim 1 , wherein the soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells is based on a combination of the soft data associated with the program state of the first memory cell and the soft data associated with the program state of the second memory cell.
4. The apparatus of claim 1 , wherein the number of program states is L and wherein log 2 (L) is a non-integer number.
5. The apparatus of claim 1 , wherein:
the number of program states is three; and
the number of data states is eight.
6. The apparatus of claim 1 , wherein:
the array includes a third memory cell programmable to one of the number of program states;
the combination of the program states further includes the program state of the third memory cell; and
the buffer and/or the controller coupled to the array is configured to:
determine soft data associated with the program state of the third memory cell; and
determine the soft data associated with the data state that corresponds to the combination of the program states based, at least in part, on the soft data associated with the program state of the third memory cell.
7. An apparatus, comprising:
an array of memory cells, wherein:
the array includes a first memory cell and a second memory cell, wherein the first and second memory cells are each programmable to one of a number of program states;
a combination of the program states of the first and second memory cells corresponds to one of a number of data states; and
a controller coupled to the array and/or a buffer included in the array configured to:
determine soft data associated with the program states of the first and second memory cells; and
determine soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program state of the first memory cell and the soft data associated with the program state of the second memory cell.
8. The apparatus of claim 7 , wherein:
the soft data associated with the program state of the first memory cell indicates a probability of whether a threshold voltage associated with the first memory cell corresponds to the program state of the first memory cell; and
the soft data associated with the program state of the second memory cell indicates a probability of whether a threshold voltage associated with the second memory cell corresponds to the program state of the second memory cell.
9. The apparatus of claim 8 , wherein:
the soft data associated with the program state of the first memory cell indicates a low, medium, or high probability of whether the threshold voltage associated with the first memory cell corresponds to the program state of the first memory cell; and
the soft data associated with the program state of the second memory cell indicates a low, medium, or high probability of whether the threshold voltage associated with the second memory cell corresponds to the program state of the second memory cell.
10. The apparatus of claim 7 , wherein the controller and/or the buffer is configured to:
combine the soft data associated with the program states of the first and second memory cells; and
determine the soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based on the combination of the soft data associated with the program state of the first memory cell and the soft data associated with the program state of the second memory cell.
11. The apparatus of claim 7 , wherein the buffer is a page buffer.
12. An apparatus, comprising:
an array of memory cells, wherein:
the array includes a first page of memory cells and a second page of memory cells, wherein each of the memory cells of the first and second pages are programmable to one of a number of program states; and
a combination of the program states of one of the memory cells of the first page and one of the memory cells of the second page corresponds to one of a number of data states; and
a buffer and/or a controller coupled to the array and configured to:
determine soft data associated with the program states of the one of the memory cells of the first page and the one of the memory cells of the second page; and
determine soft data associated with the data state that corresponds to the combination of the program states of the one of the memory cells of the first page and the one of the memory cells of the second page based, at least in part, on the soft data associated with the program state of the one of the memory cells of the first page and the soft data associated with the program state of the one of the memory cells of the second page.
13. The apparatus of claim 12 , wherein:
the first page is a first physical page of memory cells; and
the second page is a second physical page of memory cells.
14. The apparatus of claim 12 , wherein:
the first page is an even page of memory cells; and
the second page is an odd page of memory cells.
15. The apparatus of claim 12 , wherein each of the number of program states corresponds to a different logical page of data.
16. The apparatus of claim 12 , wherein the buffer is configured to determine the soft data associated with the program states of the one of the memory cells of the first page and the one of the memory cells of the second page.
17. The apparatus of claim 12 , wherein the controller is configured to determine the soft data associated with the program states of the one of the memory cells of the first page and the one of the memory cells of the second page.
18. An apparatus, comprising:
an array of memory cells programmable to a number of program states, with combinations of the number of program states corresponding to a number of data states; and
a buffer and/or a controller coupled to the array and configured to control:
determining a program state of each of at least two memory cells and soft data associated therewith;
determining a data state corresponding to a combination of the determined program states of the at least two memory cells; and
determining soft data corresponding to the determined data state based, at least partially, on a combination of the determined soft data associated with the determined program states of the at least two memory cells.
19. The apparatus of claim 18 , wherein the memory cells of the array are fractional bit memory cells.
20. The apparatus of claim 18 , wherein the memory cells of the array are flash memory cells.
21. A method of operating memory, comprising:
determining soft data associated with a program state of a first memory cell;
determining soft data associated with a program state of a second memory cell;
combining the determined soft data associated with the program state of the first memory cell with the determined soft data associated with the program state of the second memory cell to determine soft data associated with a determined data state corresponding to a combination of the program state of the first memory cell and the program state of the second memory cell.
22. The method of claim 21 , wherein the soft data associated with the determined data state corresponding to the combination of the program state of the first memory cell and the program state of the second memory cell indicates a location of a threshold voltage associated with the first memory cell within a threshold voltage distribution associated with the program state of the first memory cell and a location of a threshold voltage associated with the second memory cell within a threshold voltage distribution associated with the program state of the second memory cell.
23. The method of claim 21 , wherein the soft data associated with the determined data state corresponding to the combination of the program state of the first memory cell and the program state of the second memory cell indicates a probability of whether a threshold voltage associated with the first memory cell corresponds to the program state of the first memory cell and a probability of whether a threshold voltage associated with the second memory cell corresponds to the program state of the second memory cell.
24. The method of claim 23 , wherein the soft data associated with the determined data state corresponding to the combination of the program state of the first memory cell and the program state of the second memory cell indicates a very low, low, medium, or high probability of whether the threshold voltage associated with the first memory cell corresponds to the program state of the first memory cell and a very low, low, medium, or high probability of whether the threshold voltage associated with the second memory cell corresponds to the program state of the second memory cell.
25. The method of claim 21 , wherein the method includes:
determining the soft data associated with the program state of the first memory cell and the soft data associated with the program state of the second memory cell by a controller of the memory; and
combining the determined soft data associated with the program state of the first memory cell with the determined soft data associated with the program state of the second memory cell by the controller.
26. The method of claim 21 , wherein the method includes:
determining the soft data associated with the program state of the first memory cell and the soft data associated with the program state of the second memory cell by a buffer of an array of memory cells that includes the first and second memory cells; and
combining the determined soft data associated with the program state of the first memory cell with the determined soft data associated with the program state of the second memory cell by the buffer.
27. A method of operating memory, comprising:
determining soft data associated with a program state of a memory cell of a first page of memory cells and soft data associated with a program state of a memory cell of a second page of memory cells, wherein:
the program state of the memory cell of the first page is one of a number of program states;
the program state of the memory cell of the second page is one of a number of program states; and
a combination of the program state of the memory cell of the first page and the program state of the memory cell of the second page corresponds to one of a number of data states; and
determining soft data associated with the data state that corresponds to the combination of the program state of the memory cell of the first page and the program state of the memory cell of the second page by combining the soft data associated with the program state of the memory cell of the first page and the soft data associated with the program state of the memory cell of the second page.
28. The method of claim 27 , wherein the method includes determining the soft data associated with the program state of the memory cell of the first page and the soft data associated with the program state of the memory cell of the second page by performing a read operation on the memory cell of the first page and the memory cell of the second page.
29. The method of claim 28 , wherein the method includes determining the program state of the memory cell of the first page and the program state of the memory cell of the second page by performing the read operation on the memory cell of the first page and the memory cell of the second page.
30. The method of claim 28 , wherein performing the read operation on the memory cell of the first page and the memory cell of the second page includes executing a read command on the memory cell of the first page and the memory cell of the second page.
31. The method of claim 30 , wherein the read command includes:
a first command to read the memory cell of the first page; and
a second command to read the memory cell of the second page.
32. A method of operating memory, comprising:
determining soft data associated with a program state of a first memory cell and soft data associated with a program state of a second memory cell, wherein:
the program states of the first and second memory cells are respective ones of a number of program states; and
a combination of the program states of the first and second memory cells corresponds to one of a number of data states;
combining the soft data associated with the program state of the first memory cell and the soft data associated with the program state of the second memory cell; and
determining soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the combination of the soft data associated with the program state of the first memory cell and the soft data associated with the program state of the second memory cell.
33. The method of claim 32 , wherein the combination of the soft data associated with the program state of the first memory cell and the soft data associated with the program state of the second memory cell corresponds to one of a number of soft data combinations.
34. The method of claim 33 , wherein the one of the number of soft data combinations corresponds to the soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells.
35. The method of claim 33 , wherein the number of combinations is at least six.
36. The method of claim 33 , wherein the one of the number of soft data combinations corresponds to an additional combination of soft data associated with the program state of the first memory cell and soft data associated with the program state of the second memory cell.
37. The method of claim 33 , wherein the one of the number of soft data combinations does not correspond to any additional combinations of soft data associated with the program state of the first memory cell and soft data associated with the program state of the second memory cell.