Reversing a potential polarity for reading phase-change cells to shorten a recovery delay after programming
A potential supplied to selected cells in a Phase Change Memory (PCM) is reversed in polarity following a program operation to suppress a recovery time and provide device stabilization for a read operation.
1. A storage system, comprising:
memory cells commonly connected to a program line in a column of a memory array, each of the memory cells having a selector device and a storage device coupled in series, the selector device having a first conduction terminal and a second conduction terminal, the second conduction terminal commonly connected to a read line to receive a first voltage potential during a read operation and the first conduction terminal commonly connected to the program line via the storage device to receive a ground potential during the read operation; the second conduction terminal commonly connected to the read line to receive the ground potential during a program operation and the first conduction terminal commonly connected to the program line via the storage device to receive a second voltage potential during the program operation, the program operation being selectable from a set state and a reset state.
2. The storage system of claim 1 , wherein a value of the second voltage potential is greater than a value of the first voltage potential.
3. The storage system of claim 1 , wherein the first voltage potential to be received by the read line is a potential greater than the ground potential during a read operation of the storage system.
4. The storage system of claim 1 , wherein the first voltage potential to be received by the read line is in a range of 0.2 to 0.4 volts during the read operation of the storage system.
5. The storage system of claim 1 , wherein the first voltage potential to be applied to the read line following the second voltage potential to be applied to the program line is to reduce a recovery time by providing a reverse current flow to the selector device after programming.
6. A storage cell, comprising:
a selector device having a first conduction terminal coupled to a first terminal of a storage element and to a program line via the storage element, a second terminal of the storage element is to receive a first positive potential through the program line during a program operation and a ground potential through the program line during a read operation, a second conduction terminal of the selector device is coupled to a read line to receive the ground potential during the program operation and a second positive potential during the read operation, the program operation being selectable from a set state and a reset state.
7. The storage cell of claim 6 wherein the second positive potential is to be received following the programming operation to reduce a recovery time of the storage cell.
8. The storage cell of claim 6 wherein the second positive potential is to provide a reverse polarity to the selector device after programming.
9. The storage cell of claim 6 wherein the selector device is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device.
10. The storage cell of claim 6 wherein the selector device is an Ovonic Threshold Switch (OTS).
11. The storage cell of claim 6 wherein the storage element is chalcogenide material used in Phase-Change Memory (PCM).
12. A Phase-Change Memory (PCM), comprising:
a memory cell having a first terminal connected to a source of a selector device and a second terminal connected to a chalcogenide material, the selector device and the chalcogenide material being coupled in series, the first terminal and the second terminal being configured to have values of voltage potentials coupled thereto such that current flowing through the selector device and the chalcogenide material is reversed in direction following a program operation to suppress a recovery time and provide stabilization for a read operation, the first terminal being configured to receive a ground potential during the program operation of the PCM and the second terminal is configured to receive a positive voltage potential during the program operation, the first terminal being further configured to receive a positive voltage potential during the read operation of the PCM and the second terminal is configured to receive a ground potential during the read operation.
13. A wireless communication system, comprising:
a transceiver; and
a first processor core and a second processor core each coupled to the transceiver, the first processor core to store information in an embedded Phase-Change Memory (PCM) having memory cells that include a selector device and a chalcogenide material coupled in series between a first terminal and a second terminal, the selector device and the chalcogenide material to receive a first voltage potential in a read operation and a second voltage potential in a programming operation, the second voltage potential to cause current to flow through the selector device and the chalcogenide material in a direction opposite a current flow induced by the first voltage potential applied during the read operation, the first terminal being configured to receive a ground potential during the programming operation of the PCM and the second terminal is configured to receive a positive voltage potential during the programming operation, the first terminal being further configured to receive a positive voltage potential during the read operation of the PCM and the second terminal is configured to receive the ground potential during the read operation.
14. The wireless communication system of claim 13 , wherein the second terminal is to receive the first voltage potential in a range of 1.0 to 5.0 volts during the programming operation of the PCM.
15. The wireless communication system of claim 13 , wherein the first terminal is to receive a positive voltage potential in a range of 0.2 to 0.4 volts during the read operation of the PCM.
16. A storage cell, comprising:
a storage element having a first terminal and a second terminal; and
a selector device having a first conduction terminal coupled to the first terminal of the storage element, the second terminal of the storage element being configured to receive a first positive voltage potential during a program operation and a ground potential during a read operation, a second conduction terminal of the selector device being configured to receive the ground potential via the first conduction terminal during the program operation and a second positive voltage potential via the first conduction terminal during the read operation, the program operation being selectable from a set state and a reset state.