System and method for processing signals in high speed DRAM
The embodiments described herein provide memory devices. In one embodiment, a memory device includes bank control logic configured to generate a modified bank address signal and an active driver configured to provide a bank activate signal, receive an activate command signal, execute an activate command of the activate command signal at each one of a group of clock cycles, in which each one of the group of clock cycles is greater than one clock cycle, and receive the modified bank address signal, in which the modified bank address signal is high for at least a portion of each one of the group of clock cycles and the at least a portion of each one of the group of clock cycles is greater than one clock cycle.
1. A memory device, comprising:
bank control logic configured to generate a modified bank address signal by passing a bank address and a delayed bank address signal through an OR gate, wherein the delayed bank address signal is a time delayed version of the bank address signal; and
an active driver configured to:
provide a bank activate signal;
receive an activate command signal and execute an activate command of the activate command signal at each one of a group of clock cycles, wherein each one of the group of clock cycles is greater than one clock cycle; and
receive the modified bank address signal, wherein the modified bank address signal is high for at least a portion of each one of the group of clock cycles, and wherein the at least a portion of each one of the group of clock cycles is greater than one clock cycle.
2. The memory of claim 1 , wherein the modified bank address signal transitions to a high state at a first time and transitions to a low state at a second time, and the activate command transitions to a high state at a third time and transitions to a low state at a fourth time;
wherein the third time is after the first time, and wherein the second time is after the fourth time.
3. The memory of claim 2 , wherein a difference between the second time and the first time is greater than one clock cycle.
4. The memory device of claim 1 , comprising a command decoder configured to transmit the activate command signal to the active driver.
5. The memory device of claim 4 , wherein the command decoder is configured to transmit the activate command after each one of a group of clock cycles.
6. The memory device of claim 5 , comprising control logic, wherein the control logic comprises the command decoder and the active driver.
7. The memory device of claim 1 , wherein the bank control logic is further configured to transmit the modified bank address signal to the active driver.
8. The memory device of claim 1 , wherein the memory device is a DDR3 SDRAM memory device.
9. The memory device of claim 1 , wherein the memory device is a DDR2 SDRAM memory device.
10. The memory device of claim 1 , wherein each one of the group of clock cycles comprises four clock cycles.
11. A memory device, comprising:
bank control logic configured to generate a modified bank address signal by latching a bank address to itself;
an active driver configured to:
provide a bank activate signal;
receive an activate command signal and execute an activate command of the activate command signal at each one of a group of clock cycles, wherein each one of the group of clock cycles is greater than one clock cycle; and
receive the modified bank address signal, wherein the modified bank address signal is high for at least a portion of each one of the group of clock cycles, and wherein the at least a portion of each one of the group of clock cycles is greater than one clock cycle.
12. The memory of claim 11 , wherein the modified bank address signal transitions to a high state at a first time and transitions to a low state at a second time, and the activate command transitions to a high state at a third time and transitions to a low state at a fourth time;
wherein the third time is after the first time, and wherein the second time is after the fourth time.
13. The memory of claim 12 , wherein a difference between the second time and the first time is greater than one clock cycle.
14. The memory device of claim 11 , wherein the active driver comprises an inverter.
15. The memory device of claim 11 , comprising a row decoder configured to receive the bank activate signal from the active driver.
16. The memory device of claim 11 , wherein the active driver is configured to receive a refresh signal.
17. The memory device of claim 11 , wherein the activate command executes on every first duration of each one of the group of clock cycles.
18. The memory device of claim 11 , wherein the modified bank address signal is high for at least one or more clock cycles and for a time between successive activate commands.
19. A memory device, comprising:
an active driver comprising a NOR gate and an AND gate, wherein the active driver is configured to:
provide a bank activate signal;
receive an activate command signal, wherein an activate command of the activate command signal is configured to execute at each one of a group of clock cycles, wherein each one of the group of clock cycles is greater than one clock cycle; and
receive a bank address signal, wherein the bank address signal is high for at least a portion of each one of the group of clock cycles, and wherein the at least a portion of each one of the group of clock cycles is greater than one clock cycle;
wherein the AND gate is configured to receive the activate command signal and the bank signal, and the NOR gate is configured to receive an output of the AND gate and a refresh signal.
20. The memory device of claim 19 , wherein the active driver comprises an inverter configured to receive an output of the NOR gate.