Buried metal-semiconductor alloy layers and structures and methods for fabrication thereof
A method for forming a metal-semiconductor alloy layer uses particular thermal annealing conditions to provide a stress free metal-semiconductor alloy layer through interdiffusion of a buried semiconductor material layer and a metal-semiconductor alloy forming metal layer that contacts the buried semiconductor material layer within an aperture through a capping layer beneath which is buried the semiconductor material layer. A resulting semiconductor structure includes the metal-semiconductor alloy layer that further includes an interconnect portion beneath the capping layer and a contiguous via portion that penetrates at least partially through the capping layer. Such a metal-semiconductor alloy layer may be located interposed between a substrate and a semiconductor device having an active doped region.
1. A method for forming a metal-semiconductor alloy layer comprising:
forming an aperture completely through at least one capping layer that covers a semiconductor material layer located interposed between a substrate and the capping layer;
forming a metal-semiconductor alloy forming metal layer into the aperture and contacting the semiconductor material layer; and
thermally annealing the metal-semiconductor alloy forming metal layer and the semiconductor material layer to form a metal-semiconductor alloy layer that encroaches laterally and vertically with respect to the aperture.
2. The method of claim 1 wherein the metal-semiconductor alloy layer is formed without significant stress.
3. The method of claim 1 wherein the semiconductor material layer is included within a microelectronic structure selected from the group consisting of a purely electronic microelectronic structure, a microelectromechanical system (MEMS) structure and an optoelectronic structure.
4. The method of claim 1 wherein the semiconductor material layer comprises a semiconductor material selected from the group consisting of an amorphous semiconductor material, a polycrystalline semiconductor material and a monocrystalline semiconductor material.
5. The method of claim 1 wherein:
the metal-semiconductor alloy layer comprises a nickel metal-semiconductor alloy material; and
the thermal annealing is undertaken at a temperature from about 450 to about 600 degrees centigrade.
6. The method of claim 1 , further comprising forming a semiconductor material layer adjoining the metal-semiconductor alloy layer.
7. The method of claim 1 wherein the metal-semiconductor alloy layer comprises a metal-semiconductor alloy forming metal selected from the group consisting of nickel, cobalt, copper, iron, titanium, tungsten, erbium, ytterbium, platinum and vanadium metal-semiconductor alloy forming metals.
8. The method of claim 1 wherein the metal-semiconductor alloy layer is included within at least one of a purely electronic microelectronic structure, a microelectromechanical system (MEMS) structure and an optoelectronic structure.
9. The method of claim 1 , wherein the substrate comprises a source/drain region.
10. The method of claim 1 , wherein the metal semiconductor alloy layer is an interconnect.