IP Library Granted Patent US 8,765,508
Granted Patent B2
US 8,765,508 · App. 13/060,398 · Granted Jul 1, 2014

Methods of fabricating semiconductor structures or devices using layers of semiconductor material having selected or controlled lattice parameters

Inventor: Chantal Arena (Mesa, AZ)
Assignee: Soitec
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Quick Facts
Patent No.
US 8,765,508
App. No.
13/060,398
Granted
Jul 1, 2014
Kind
B2
Abstract

Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature.

Claims (25)

1. A method of fabricating a semiconductor structure or device, comprising:

changing a temperature of a layer of semiconductor material attached to a base substrate from a first temperature to a second temperature, wherein the base substrate has a selected coefficient of thermal expansion that is different from a coefficient of thermal expansion of the layer of semiconductor material;

causing a lattice parameter of the layer of semiconductor material to change from a first value to a second value while changing the temperature of the layer of semiconductor material from the first temperature to the second temperature;

bonding the layer of semiconductor material to another layer of material while the layer of semiconductor material is at the second temperature;

removing the bonded layer of semiconductor material and the another layer of material from the base substrate;

returning the temperature of the layer of semiconductor material to the first temperature after bonding the layer of semiconductor material to the another layer of material and removing the bonded layer of semiconductor material and the another layer of material from the base substrate; and

growing at least one additional layer of semiconductor material on the layer of semiconductor material;

wherein the another layer of material has a selected coefficient of thermal expansion lower than a coefficient of thermal expansion of the base substrate, such that the another layer of material prevents the lattice parameter of the layer of semiconductor material from returning to the first value upon returning the temperature of the layer of semiconductor material to the first temperature.

2. The method of claim 1 , further comprising allowing the lattice parameter of the layer of semiconductor material to change to a third value between the first value and the second value upon returning the temperature of the layer of semiconductor material to the first temperature.

3. The method of claim 1 , further comprising selecting the base substrate to comprise a base material exhibiting a coefficient of thermal expansion greater than a coefficient of thermal expansion exhibited by the layer of semiconductor material.

4. The method of claim 1 , further comprising selecting the another layer of material to comprise a material exhibiting a coefficient of thermal expansion less than the coefficient of thermal expansion exhibited by the layer of semiconductor material.

5. The method of claim 1 , further comprising selecting the layer of semiconductor material to comprise indium gallium nitride.

6. The method of claim 5 , further comprising:

selecting the at least one additional layer of semiconductor material to comprise another layer of indium gallium nitride; and

forming the another layer of indium gallium nitride to have a thickness greater than about five hundred nanometers (500 nm) and a concentration of indium greater than about five atomic percent (5 at %).

7. The method of claim 1 , further comprising:

attaching a receiving substrate on a side of the layer of semiconductor material opposite the another layer of material after removing the layer of semiconductor material and the another layer of material from the base substrate and prior to growing the at least one additional layer of semiconductor material on the layer of semiconductor material; and

removing the another layer of material from the layer of semiconductor material after attaching the receiving substrate to the layer of semiconductor material and prior to growing the at least one additional layer of semiconductor material on the layer of semiconductor material.

8. The method of claim 7 , wherein growing the at least one additional layer of semiconductor material on the layer of semiconductor material comprises:

growing a plurality of additional layers of semiconductor material on the layer of semiconductor material on a side thereof opposite the receiving substrate; and

configuring the plurality of additional layers of semiconductor material to comprise a light-emitting device.

9. The method of claim 1 , wherein changing a temperature of the layer of semiconductor material from a first temperature to a second temperature comprises heating the layer of semiconductor material to at least five hundred degrees Celsius (500° C.).

10. The method of claim 1 , wherein causing a lattice parameter of the layer of semiconductor material to change from a first value to a second value while changing the temperature of the layer of semiconductor material from the first temperature to the second temperature comprises increasing the lattice parameter of the layer of semiconductor material by greater than one-half of one percent (0.5%).

11. The method of claim 7 , further comprising selecting the receiving substrate to comprise a material exhibiting a coefficient of thermal expansion lower than the coefficient of thermal expansion of the base substrate.

12. The method of claim 11 , further comprising selecting the layer of semiconductor material to comprise a material exhibiting a coefficient of thermal expansion between the coefficient of thermal expansion of the receiving substrate and the coefficient of thermal expansion of the base substrate.

Assignments (2)
CHANGE OF NAME Recorded Feb 28, 2012
From: S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES; CHEMIN DES FRANQUES; PARC TECHNOLOGIES DES FONTAINES; BERNIN. FRANCE 38190
To: SOITEC
Reel/Frame 028138/0895 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2011
From: ARENA, CHANTAL
To: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
Reel/Frame 025852/0458 →
Continuity (2)
Provisional Application 61092373 · Aug 27, 2008
Related Publication 20110156212A1 · Jun 30, 2011