Techniques for accessing memory cells
Techniques for accessing memory cells are disclosed. In one particular embodiment, the techniques may be realized as an apparatus providing voltage to a high impedance node of a memory cell. The apparatus may comprise a precharge switch coupled to a first voltage source node, a precharge capacitor coupled to the precharge switch, and a switch matrix coupled to the precharge capacitor, a second voltage source node, and the high impedance node of the memory cell. The precharge switch may be configured to decouple the precharge capacitor from the first voltage source node, and the switch matrix may be configured to decouple the second voltage source node from the high impedance node of the memory cell and to couple the precharge capacitor to the high impedance node of the memory cell.
1. An apparatus for providing voltage to a high impedance node of a memory cell, the apparatus comprising:
a precharge switch coupled to a first voltage source node;
a precharge capacitor coupled to the precharge switch;
a switch matrix coupled to the precharge capacitor, a second voltage source node, and the high impedance node of the memory cell; and
an access controller configured to control the precharge switch and the switch matrix to provide selected voltage levels to the high impedance node of the memory cell to cause the memory cell to operate in a hold mode wherein the memory cell maintains a data state, a read mode wherein a data state is read from the memory cell, a first write mode wherein a logical low data state is written to the memory cell, and a second write mode wherein a logical high data state is written to the memory cell.
2. The apparatus of claim 1 , wherein the memory cell comprises a zero-capacitor random access memory (Z-RAM) cell.
3. The apparatus of claim 2 , wherein the high impedance node of the memory cell comprises a gate node of the Z-RAM cell.
4. The apparatus of claim 2 , wherein the first voltage source node is configured to provide a write voltage of the memory cell and the second voltage source node is configured to provide a hold voltage of the memory cell.
5. The apparatus of claim 1 , wherein the precharge capacitor comprises a parasitic capacitor of a conductive line between the precharge switch and the switch matrix.
6. The apparatus of claim 1 , wherein the precharge capacitor comprises a capacitor formed by a dummy wordline coupled to the memory cell.
7. The apparatus of claim 6 , wherein in the hold mode of operation the access controller is configured to trigger the precharge switch to couple the first voltage source node to the precharge capacitor and to trigger the switch matrix to couple the second voltage source node to the high impedance node, and wherein in the read mode of operation the access controller is configured to trigger the precharge switch to decouple the first voltage source node from the precharge capacitor and to trigger the switch matrix to couple the precharge capacitor to the high impedance node.
8. The apparatus of claim 6 , wherein in the write mode of operation the access controller is configured to trigger the precharge switch and the switch matrix to couple the first voltage source node to the precharge capacitor and the high impedance node, wherein in the hold mode of operation the access controller is configured to trigger the precharge switch to decouple the first voltage source node from the precharge capacitor, to trigger the switch matrix to decouple the high impedance node from the precharge capacitor, and to trigger the switch matrix to couple the high impedance node to the second voltage source node, and wherein in the read mode of operation the access controller is configured to trigger the switch matrix to decouple the high impedance node from the second voltage source and to couple the precharge capacitor to the high impedance node.
9. The apparatus of claim 1 , wherein the switch matrix comprises a first switch and a second switch, wherein the first switch and the second switch are connected in series, and wherein one node of the first switch is coupled to the precharge capacitor, one node of the second switch is coupled to the second voltage source node, and a common node of the first switch and the second switch is coupled to the high impedance node of the memory cell.
10. The apparatus of claim 1 , wherein the precharge switch comprises a tri-state logic gate.
11. The apparatus of claim 1 , wherein the precharge switch comprises a transmission gate.
12. The apparatus of claim 1 , wherein the precharge capacitor comprises a wordline bus, wherein the precharge switch comprises a first demultiplexer coupled to the wordline bus, and further wherein the switch matrix comprises a second multiplexer configured to couple the wordline bus to the high impedance node.
13. A memory apparatus comprising:
a memory cell array having a plurality of memory cells;
a wordline coupled to a high impedance node of one of the plurality of memory cells in the memory cell array;
a precharge switch coupled to a first voltage source node;
a precharge capacitor coupled to the precharge switch;
a switch matrix coupled to the precharge capacitor, a second voltage source node, and the high impedance node of the memory cell; and
an access controller configured to control the precharge switch and the switch matrix to provide selected voltage levels to the high impedance node of the memory cell to cause the memory cell to operate in a hold mode wherein the memory cell maintains a data state, a read mode wherein a data state is read from the memory cell, a first write mode wherein a logical low data state is written to the memory cell, and a second write mode wherein a logical high data state is written to the memory cell.
14. The memory apparatus of claim 13 , wherein the precharge capacitor comprises a parasitic capacitor of a conductive line between the precharge switch and the switch matrix.
15. The memory apparatus of claim 13 , wherein the precharge capacitor comprises a capacitor formed by a dummy wordline coupled to one or more memory cells in the memory cell array.
16. The memory apparatus of claim 13 , wherein the precharge switch comprises a tri-state logic gate.
17. The memory apparatus of claim 13 , wherein the switch matrix comprises a first switch and a second switch, wherein the first switch and the second switch are connected in series, and wherein one node of the first switch is coupled to the precharge capacitor, one node of the second switch is coupled to the second voltage source node, and a common node of the first switch and the second switch is coupled to the high impedance node of the memory cell.
18. The memory apparatus of claim 17 , wherein the first switch and the second switch each comprises a respective transmission gate.
19. The memory apparatus of claim 13 , wherein the precharge capacitor comprises a capacitor formed by a dummy wordline coupled to the memory cell.
20. The memory apparatus of claim 19 , wherein in the hold mode of operation the access controller triggers the precharge switch to couple the first voltage source node to the precharge capacitor and triggers the switch matrix to couple the second voltage source node to the high impedance node, and wherein in the read mode of operation the access controller triggers the precharge switch to decouple the first voltage source node from the precharge capacitor and triggers the switch matrix to couple the precharge capacitor to the high impedance node.
21. The memory apparatus of claim 19 , wherein in the write mode of operation the access controller is configured to trigger the precharge switch and the switch matrix to couple the first voltage source node to the precharge capacitor and the high impedance node, wherein in the hold mode of operation the access controller is configured to trigger the precharge switch to decouple the first voltage source node from the precharge capacitor, to trigger the switch matrix to decouple the high impedance node from the precharge capacitor, and to trigger the switch matrix to couple the high impedance node to the second voltage source node, and wherein in the read mode of operation the access controller is configured to trigger the switch matrix to decouple the high impedance node from the second voltage source and to couple the precharge capacitor to the high impedance node.
22. The memory apparatus of claim 13 , wherein the precharge capacitor comprises a wordline bus, wherein the precharge switch comprises a first demultiplexer coupled to the wordline bus, and further wherein the switch matrix comprises a second multiplexer configured to couple the wordline bus to the high impedance node.
23. Logic encoded on one or more non-transitory media for execution and when executed operable to provide a desired voltage to a high impedance node of a memory cell, the logic operable to:
trigger a precharge switch to couple a precharge capacitor to a first voltage source to charge the precharge capacitor to a first voltage, trigger a switch matrix to decouple the high impedance node of the memory cell from a second voltage source, and trigger the switch matrix to couple the precharge capacitor to the high impedance node of the memory cell to charge the high impedance node of the memory cell to the first voltage source during a write operation performed on the memory cell;
trigger the switch matrix to decouple the precharge capacitor from the high impedance node of the memory cell and trigger the switch matrix to couple the high impedance node of the memory cell to the second voltage source to charge the high impedance node of the memory cell to a second voltage during a hold operation performed on the memory cell; and
trigger the precharge switch to decouple the precharge capacitor from the first voltage source, trigger the switch matrix to decouple the high impedance node of the memory cell from the second voltage source, and trigger the switch matrix to couple the precharge capacitor to the high impedance node of the memory cell to charge the high impedance node of the memory cell to a third voltage that is a result of charge sharing between precharge capacitor and the high impedance node of the memory cell during a read operation performed on the memory cell.
24. The logic of claim 23 , wherein the precharge capacitor comprises a capacitor bank that can be configured to provide a selected capacitance.
25. The logic of claim 24 , further operable to configure the capacitor bank to provide the desired voltage to the high impedance node of the memory cell.
26. The logic of claim 23 , wherein the precharge switch comprises a tri-state logic gate.
27. The logic of claim 23 , wherein the precharge capacitor comprises a wordline bus, wherein the precharge switch comprises a first demultiplexer coupled to the wordline bus, and further wherein the switch matrix comprises a second multiplexer configured to couple the wordline bus to the high impedance node.