Solid-state image pickup device
A solid-state image pickup device 1 according to the present invention includes a semiconductor substrate 2 on which a pixel 20 composed of a photodiode 3 and a transistor is formed. The transistor comprising the pixel 20 is formed on the surface of the semiconductor substrate, a pn junction portion formed between high concentration regions of the photodiode 3 is provided within the semiconductor substrate 2 and a part of the pn junction portion of the photodiode 3 is extended to a lower portion of the transistor formed on the surface of the semiconductor substrate 2 . According to the present invention, there is provided a solid-state image pickup device in which a pixel size can be microminiaturized without lowering a saturated electric charge amount (Qs) and sensitivity.
1. A solid-state image pickup device comprising:
a pixel composed of a photodiode and a transistor; and
a semiconductor substrate with said pixel formed thereon,
wherein a pn junction portion formed between high concentration regions of said photodiode is formed within said semiconductor substrate and a part of said pn junction portion of said photodiode is extended to a lower portion of said transistor formed on the surface of said semiconductor substrate,
wherein said pixel includes a charge readout transistor for reading out signal electric charges from said photodiode, a channel portion of said charge readout transistor being formed in the depth direction of the surface of said semiconductor substrate.
2. A solid-state image pickup device according to claim 1 , wherein said charge readout transistor includes a gate electrode and a gate insulating film, the bottom portions of which are formed at the position deeper than the depth of said pn junction portion of said photodiode.
3. An imaging device comprising:
a photodiode between a surface side of a semiconductor substrate and a back side of the semiconductor substrate, said photodiode including a first region of a first conductivity type and a second region of a second conductivity type; and
a charge readout transistor extending from the surface side of the semiconductor substrate to a depth reaching a portion of the second region, the first region being closer to the surface side of the semiconductor substrate than the second region,
wherein at least a bottom portion of the charge readout transistor touches a third region of the first conductivity type.
4. The device of claim 3 , further comprising:
a floating diffusion region adjacent to the charge readout transistor at the surface side of the semiconductor substrate.
5. The device of claim 3 , wherein the charge readout transistor includes a gate electrode and a gate insulating film formed in a groove.
6. The device of claim 5 , wherein at least the bottom portion and a portion of sidewalls of the groove are surrounded by the third region.
7. The device of claim 6 , wherein the third region has lower impurity concentration of the first conductivity type than that of the first region.
8. The device of claim 3 , wherein the back side of the semiconductor substrate is a light incident side.
9. The device of claim 3 , further comprising:
a reset transistor and an amplifying transistor.
10. The device of claim 3 , wherein the first conductivity type is a p-type and the second conductivity type is an n-type.