IP Library Granted Patent US 8,785,989
Granted Patent B2
US 8,785,989 · App. 13/108,847 · Granted Jul 22, 2014

Semiconductor constructions

Inventors: Lucien J. Bissey (Boise, ID); William A. Stanton (Boise, ID)
Assignee: Micron Technology, Inc.
G03F7/0035H01L21/76897H01L21/31144H01L21/312
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,785,989
App. No.
13/108,847
Granted
Jul 22, 2014
Kind
B2
Abstract

The invention includes semiconductor constructions containing optically saturable absorption layers. An optically saturable absorption layer can be between photoresist and a topography, with the topography having two or more surfaces of differing reflectivity relative to one another. The invention also includes methods of patterning photoresist in which a saturable absorption layer is provided between the photoresist and a topography with surfaces of differing reflectivity, and in which the differences in reflectivity are utilized to enhance the accuracy with which an image is photolithographically formed in the photoresist.

Claims (32)

1. A semiconductor construction, comprising:

a semiconductor substrate;

in at least one cross-sectional view, spaced projections over the substrate, the spaced projections being spaced from one another by an intervening region;

a first layer over the spaced projections and over the intervening region between the spaced projections, at least one of the following two uppermost surfaces terminating at a bottommost surface of the first layer: an uppermost surface of respective space projections and an uppermost surface of an intervening region;

an optically saturable absorption layer over the first layer;

photoresist over the optically saturable absorption layer; and

wherein the spaced projections correspond to an upwardly-opening container structure, and wherein the intervening region comprises insulative material within the container structure.

2. The construction of claim 1 wherein the spaced projections comprise conductively-doped silicon capped with metal silicide.

3. The construction of claim 1 wherein the spaced projections correspond to pedestals, and wherein the intervening region comprises a transistor gate stack.

4. The construction of claim 1 wherein the optically saturable absorption layer comprises a plurality of optically saturable absorption layers.

5. The construction of claim 1 further comprising a source/drain for a transistor, the source/drain in contact with one of the spaced projections.

6. The construction of claim 1 further comprising a capacitor storage node in contact with at least one of the following: the spaced projections, the first layer and material in the intervening region.

7. A semiconductor construction, comprising:

a semiconductor substrate;

in at least one cross-sectional view, spaced projections over the substrate, the spaced projections being spaced from one another by an intervening region;

a first layer over the spaced projections and over the intervening region between the spaced projections;

an optically saturable absorption layer over the first layer;

photoresist over the optically saturable absorption layer;

a capacitor storage node in contact with one of the spaced projections; and

wherein the capacitor storage node is located only in material in the intervening region.

8. The construction of claim 7 wherein the capacitor storage node is further in contact with at least one of the following: the first layer and material in the intervening region.

9. The construction of claim 8 wherein the capacitor storage node is further in contact with both of the first layer and the material in the intervening region.

10. A semiconductor construction, comprising:

a semiconductor substrate;

in at least one cross-sectional view, spaced projections over the substrate, the spaced projections being spaced from one another by an intervening region;

a first layer over the spaced projections and over the intervening region between the spaced projections;

an optically saturable absorption layer over the first layer;

photoresist over the optically saturable absorption layer; and

an opening for a capacitor storage node, the opening extends through at least two of the following: material in the intervening region, the first layer, the optically saturable absorption layer and the photoresist.

11. The construction of claim 10 further comprising capacitor storage node material in only the material of the intervening region.

12. The construction of claim 10 wherein the opening extends into at least three of the following: the material of the intervening region, the first layer, the optically saturable absorption layer and the photoresist.

13. The construction of claim 10 further comprising capacitor storage node material in contact with one of the spaced projections and wherein the opening is over the capacitor storage node material.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (3)
Division 12196114 · Aug 21, 2008
Continuation 11341201 · Jan 27, 2006
Related Publication 20110215387A1 · Sep 8, 2011