Memory system having delay-locked-loop circuit
A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.
1. A memory system, comprising:
a memory controller; and
a semiconductor memory device configured to transmit data to or receive data from the memory controller,
wherein the semiconductor memory device comprises:
a first delay-locked-loop (DLL) configured to adjust a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a first frequency; and
a second DLL configured to adjust the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a second frequency,
wherein the second DLL is configured to operate in response to a mode register set signal.
2. The memory system as claimed in claim 1 , wherein the first frequency is a low frequency and the second frequency is a high frequency.
3. The memory system as claimed in claim 1 , wherein the first DLL is configured to operate in response to the mode register set signal.