Through-substrate vias and methods for forming the same
View Patent ↗A device includes a semiconductor substrate and a Metal-Oxide-Semiconductor (MOS) transistor. The MOS transistor includes a gate electrode over the semiconductor substrate, and a source/drain region on a side of the gate electrode. A source/drain contact plug includes a lower portion and an upper portion over the lower portion, wherein the source/drain contact plug is disposed over and electrically connected to the source/drain region. A gate contact plug is disposed over and electrically connected to the gate electrode, wherein a top surface of the gate contact plug is level with a top surface of the top portion of the source/drain contact plug. A Through-Substrate Via (TSV) extends into the semiconductor substrate. A top surface of the TSV is substantially level with an interface between the gate contact plug and the gate electrode.
1. A device comprising:
a semiconductor substrate;
a Metal-Oxide-Semiconductor (MOS) transistor comprising:
a gate electrode over the semiconductor substrate; and
a source/drain region on a side of the gate electrode;
a source/drain contact plug comprising a lower portion and an upper portion over the lower portion, wherein the source/drain contact plug is over and electrically connected to the source/drain region;
a gate contact plug over and electrically connected to the gate electrode, wherein a top surface of the gate contact plug is level with a top surface of the upper portion of the source/drain contact plug; and
a Through-Substrate Via (TSV) extending into the semiconductor substrate, wherein a top surface of the TSV is level with an interface between the gate contact plug and the gate electrode.
2. The device of claim 1 further comprising:
an inter-layer dielectric over the semiconductor substrate, wherein the gate electrode and the lower portion of the source/drain contact plug comprise portions in the inter-layer dielectric; and
an etch stop layer over and contacting the inter-layer dielectric, wherein the top surface of the TSV is in contact with the etch stop layer.
3. The device of claim 2 , wherein the gate contact plug and the upper portion of the source/drain contact plug penetrate through the etch stop layer.
4. The device of claim 1 further comprising a via and a metal line over the via, wherein the via and the metal line form a dual damascene structure, and wherein a bottom surface of the via is in contact with a top surface of the gate contact plug.
5. The device of claim 4 further comprising:
an inter-layer dielectric over the gate electrode, wherein the upper portion of the source/drain contact plug comprises a portion disposed in the inter-layer dielectric; and
an etch stop layer over the inter-layer dielectric, wherein the via extends into the etch stop layer.
6. The device of claim 1 , wherein the upper portion and the lower portion of the source/drain contact plug have a distinguishable interface.
7. The device of claim 1 further comprising a TSV contact plug over and contacting the TSV, wherein the TSV contact plug is at a same level as the gate contact plug.
8. The device of claim 1 , wherein the TSV comprises:
an insulation layer in contact with the semiconductor substrate;
a diffusion barrier layer over the insulation layer; and
a metallic material over the diffusion barrier layer, wherein each of the insulation layer, the diffusion barrier layer, and the metallic material extend from the interface into the semiconductor substrate.