Unique mark and method to determine critical dimension uniformity and registration of reticles combined with wafer overlay capability

1. A method for wafer processing, comprising:

accepting alignment information for at least one pattern on at least one layer of a semiconductor device determined from a combined metrology mark including:

a wafer overlay mark structure configured to provide alignment information between two different patterns on at least two successive layers of a substrate;

a mask misregistration structure configured to provide alignment information between two different patterns on a same layer and disposed at least partially within a perimeter of the wafer overlay mark structure;

calculating alignment error; and

presenting a calculated correlation between mask data and wafer data.

2. The method of claim 1 , wherein the accepting alignment information for at least one pattern on at least one layer of a semiconductor device determined from a combined metrology mark including a mask misregistration structure and a wafer overlay mark structure comprises:

accepting alignment information for at least one pattern on at least one layer of a semiconductor device determined from a combined metrology mark including at least one of a mask misregistration structure and a wafer overlay mark structure including a grating based mark.

3. The method of claim 2 , wherein the accepting alignment information for at least one pattern on at least one layer of a semiconductor device determined from a combined metrology mark including at least one of a mask misregistration structure and a wafer overlay mark structure including a grating based mark comprises:

accepting alignment information for at least one pattern on at least one layer of a semiconductor device determined from a combined metrology mark including at least one of a mask misregistration structure and a wafer overlay mark structure including at least two rectangular working zones, where a first set of working zones includes a periodic structure comprised by at least one coarsely segmented line oriented in a first direction and a second set of working zones includes a periodic structure comprised by at least one coarsely segmented line oriented in a second direction oriented orthogonally to the first direction.

4. The method of claim 1 , wherein the accepting alignment information for at least one pattern on at least one layer of a semiconductor device determined from a combined metrology mark further comprises:

accepting alignment information for at least one pattern on at least one layer of a semiconductor device determined from a combined metrology mark including a box shaped structure disposed substantially in the middle of the combined metrology mark.

5. The method of claim 4 , wherein the accepting alignment information for at least one pattern on at least one layer of a semiconductor device determined from a combined metrology mark including a box shaped structure disposed substantially in the middle of the combined metrology mark comprises:

accepting alignment information for at least one pattern on at least one layer of a semiconductor device determined from a combined metrology mark including a 1 μm contact box.

6. The method of claim 1 , wherein the accepting alignment information for at least one pattern on at least one layer of a semiconductor device determined from a combined metrology mark comprises:

accepting alignment information for at least one pattern on at least one layer of a semiconductor device determined from a combined metrology mark including a cross shaped structure disposed substantially in the middle of the combined metrology mark.

7. The method for wafer processing in claim 1 , wherein the accepting alignment information for at least one pattern on at least one layer of a semiconductor device determined from a combined metrology mark comprises:

accepting mask registration information and at least one critical dimension data file.

8. The method for wafer processing in claim 1 , wherein the calculating alignment error comprises:

converting mask registration data and critical dimension data with wafer scale and required orientation to match wafer data.

9. The method for wafer processing in claim 1 , wherein the calculating alignment error comprises:

removing at least one outlier using an algorithm.

10. The method for wafer processing in claim 1 , wherein the calculating alignment error comprises:

applying a relevant model to mask data and displaying at least one of raw data, modeled data, or residual data.

11. The method for wafer processing in claim 1 , wherein the calculating alignment error comprises:

calculating the correlation between mask data and wafer data.

12. The method for wafer processing in claim 1 , wherein the presenting a calculated correlation between mask data and wafer data comprises:

presenting mask registration information and wafer overlay information together.

13. The method for wafer processing in claim 1 , wherein the presenting a calculated correlation between mask data and wafer data comprises:

presenting mask critical dimension error information and wafer critical dimension error information together.

14. The method for wafer processing in claim 1 , wherein the presenting a calculated correlation between mask data and wafer data comprises:

presenting mask error information subsequent to subtracting at least one of wafer overlay information and critical dimension data information.

15. The method in claim 1 , further comprising:

identifying a mask registration measurement and a wafer overlay measurement;

creating a wafer overlay mark by double exposure by the scanner; and

calculating a mask registration error by subtracting a first mask registration value from a second mask registration value.

16. The method for wafer processing in claim 15 , wherein the identifying a mask registration measurement and a wafer overlay measurement comprises:

creating the mask registration measurement by exposing a single mask twice.

17. The method for wafer processing in claim 15 , wherein the creating a wafer overlay mark by double exposure by the scanner comprises:

utilizing an exposure condition combination.

18. The method in claim 1 , further comprising:

receiving mask registration error data;

receiving mask non-flatness error data; and

performing at least one of mask calibration and qualification according to the mask registration error data and the mask non-flatness error data.

19. The method in claim 18 , further comprising:

receiving image placement error data; and

performing at least one of mask calibration and qualification according to the image placement error.

20. A system comprising:

means for accepting alignment information for at least one pattern on at least one layer of a semiconductor device determined from a combined metrology mark including:

a wafer overlay mark structure configured to provide alignment information between two different patterns on at least two successive layers of a substrate, and

a mask misregistration structure configured to provide alignment information between two different patterns on a same layer and disposed at least partially within a perimeter of the wafer overlay mark structure;

means for calculating alignment error; and

means for presenting a calculated correlation between mask data and wafer data.

21. A system comprising:

a semiconductor device layer alignment detector configured for generating alignment information;

a processing device configured for:

accepting alignment information from the semiconductor device layer alignment detector associated with at least one pattern on at least one layer of a semiconductor device determined from a combined metrology mark including:

a wafer overlay mark structure configured to provide alignment information between two different patterns on at least two successive layers of a substrate;

a mask misregistration structure configured to provide alignment information between two different patterns on a same layer and disposed at least partially within a perimeter of the wafer overlay mark structure;

calculating alignment error; and

a presentation device configured for presenting a calculated correlation between mask data and wafer data.