IP Library Granted Patent US 8,815,652
Granted Patent B2
US 8,815,652 · App. 12/130,577 · Granted Aug 26, 2014

Semiconductor device and method of manufacturing the same and semiconductor manufacturing device

Inventors: Fumihiko Inoue (Aizuwakamatsu, JP); Kentaro Sera (Aizumisato-machi, JP)
Assignee: Spansion LLC
G11C17/10H01L27/112H01L27/11226
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Quick Facts
Patent No.
US 8,815,652
App. No.
12/130,577
Filed
May 30, 2008
Granted
Aug 26, 2014
Kind
B2
Art Unit
2896
USPC
438/598
Abstract

The present invention is a manufacturing method for a semiconductor device having steps of; aligning a program head 80 having a program dot array corresponding to each OTP-ROM cell array 21 provided in areas 12 to be a plurality of semiconductor chips arranged in a semiconductor wafer to the OTP-ROM cell array 21 in one of the areas to be the plurality of semiconductor chips 12 ; and programming the OTP-ROM cell array 21 with a different pattern for each of the areas to be the plurality of semiconductor chips 12 by using the program head 80.

Claims (16)

1. A method for manufacturing a semiconductor device comprising steps of:

aligning a program head, having a program dot array corresponding to each OTP-ROM cell array provided in areas to be a plurality of semiconductor chips arranged in a semiconductor wafer, to the OTP-ROM cell array in one of the areas to be the plurality of semiconductor chips; and

programming the OTP-ROM cell array with a different pattern for each of the areas to be the plurality of semiconductor chips by using the program head wherein respective different patterns are programmed for each of the plurality of semiconductor chips using respective different configurations of dots associated with the program head.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein the step of programming the OTP-ROM cell array ejects a chemical fluid that activates or inactivates a plurality of OTP-ROM cells included in the OTP-ROM cell array to the plurality of OTP-ROM cells.

3. The method for manufacturing a semiconductor device according to claim 2 , wherein the step of programming the OTP-ROM cell array activates or inactivates the plurality of OTP-ROM cells by connecting a wiring of the OTP-ROM cell array by using the chemical fluid.

4. The method for manufacturing a semiconductor device according to claim 2 , wherein the step of programming the OTP-ROM cell array activates or inactivates the plurality of OTP-ROM cells by disconnecting a wiring of the OTP-ROM cell array by using the chemical fluid.

5. The method for manufacturing a semiconductor device according to claim 1 , wherein the step of programming the OTP-ROM cell array comprises:

forming a pattern to activate or inactivate a plurality of OTP-ROM cells by irradiating a photoresist on the OTP-ROM cell array with light by using the program head; and

activating or inactivating the plurality of OTP-ROM cells by connecting or disconnecting a wiring of the OTP-ROM cell array by using the pattern.

6. The method for manufacturing a semiconductor device according to claim 1 , wherein the step of programming the OTP-ROM cell array comprises:

forming a pattern to activate or inactivate a plurality of OTP-ROM cells by irradiating a photoresist on the OTP-ROM cell array with light by using the program head; and

activating or inactivating the plurality of OTP-ROM cells by ion-implanting the plurality of OTP-ROM cells by using the pattern.

7. A semiconductor manufacturing device comprising:

a program head having a program dot array corresponding to each OTP-ROM cell array provided in areas to be a plurality of semiconductor chips arranged in a semiconductor wafer; and

an aligning portion for aligning the program head to the OTP-ROM cell array in one of the areas to be the plurality of semiconductor chips;

wherein the program head programs the OTP-ROM cell array with a different pattern for each of the areas to be the plurality of semiconductor chips wherein respective different patterns are programmed for each of the plurality of semiconductor chips using respective different configurations of dots associated with the program head.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 10, 2008
From: INOUE, FUMIHIKO; SERA, KENTARO
To: SPANSION LLC
Reel/Frame 021510/0468 →
Priority Claims (1)
JP 2007-151619 · Jun 7, 2007 · national
Continuity (1)
Related Publication 20080316790A1 · Dec 25, 2008