Structure and method for reducing floating body effect of SOI MOSFETs

1. A method of making an integrated circuit (IC) structure, comprising:

providing a silicon on insulator (SOT) substrate;

forming at least one metal oxide semiconductor field effect transistor (MOSFET) on the SOI substrate;

forming an asymmetrical source-drain junction in the at least one MOSFET by damaging a pn junction to reduce floating body effects of the at least one MOSFET;

forming an oxide layer on the SOI substrate;

depositing a poly-Si layer on the oxide layer;

depositing a nitride layer on the poly-Si layer;

patterning a gate by etching portions of the poly-Si layer and the nitride layer;

forming spacers on sides of the gate;

etching portions of the oxide layer using the nitride layer and the spacers as a mask;

etching portions of an epitaxial Si layer of the SOI substrate using the nitride layer and the spacers as a mask;

etching portions of an epitaxial SiGe layer of the SOI substrate using the nitride layer and the spacers as a mask;

depositing a second epitaxial Si layer surrounding a remaining portion of the epitaxial SiGe layer, a remaining portion of the epitaxial Si layer and planar with an upper surface of a remaining portion of the oxide layer;

etching a Si layer of the SOI substrate to expose the epitaxial SiGe layer;

planarizing the epitaxial SiGe layer;

etching portions of the epitaxial SiGe layer; and

etching portions of the second epitaxial Si layer.

2. The method of claim 1 , further comprising:

flipping the at least one MOSFET; and

bonding the at least one MOSFET to another MOSFET.

3. A method of making an integrated circuit (IC) structure, comprising:

providing a silicon on insulator (SOI) substrate;

forming at least one metal oxide semiconductor field effect transistor (MOSFET) on the SOI substrate;

forming an asymmetrical source-drain junction in the at least one MOSFET by damaging a pn junction to reduce floating body effects of the at least one MOSFET;

forming an oxide layer on the SOI substrate;

depositing a poly-Si layer on the oxide layer;

depositing a nitride layer on the poly-Si layer;

patterning a gate by etching portions of the poly-Si layer and the nitride layer;

forming spacers on sides of the gate;

etching portions of the oxide layer using the nitride layer and the spacers as a mask;

etching portions of an epitaxial Si layer of the SOI substrate using the nitride layer and the spacers as a mask;

etching portions of an epitaxial SiGe layer of the SOI substrate using the nitride layer and the spacers as a mask;

depositing a second epitaxial Si layer surrounding a remaining portion of the epitaxial SiGe layer and a remaining portion of the epitaxial Si layer and planar with a remaining portion of the oxide layer;

flipping the at least one MOSFET;

bonding the at least one MOSFET to another MOSFET;

etching a Si layer of the SOT substrate to expose the epitaxial SiGe layer;

planarizing the epitaxial SiGe layer;

etching portions of the epitaxial SiGe layer; and

etching portions of the second epitaxial Si layer.

4. The method of claim 3 , further comprising:

forming a mask over one side of the flipped at least one MOSFET; and

implanting Ge to a portion of the at least one MOSFET exposed by the mask to form a damaged pn junction.

5. The method of claim 4 , wherein the implanting Ge creates a modified epitaxial SiGe layer portion and a modified second epitaxial Si layer portion.

6. The method of claim 4 , further comprising:

depositing a second oxide layer over the epitaxial SiGe layer and the second epitaxial Si layer; and

planarizing the second oxide layer.

7. The method of claim 6 , further comprising building at least one through silicon via (TSVs) providing electrical contact between the at least one MOSFET and the another MOSFET.

8. A method comprising:

forming at least one metal oxide semiconductor field effect transistor (MOSFET) on a silicon on insulator (SOI) substrate;

masking a portion of the at least one MOSFET;

implanting a dopant in an unmasked portion of the MOSFET to form an asymmetrical source-drain junction in the at least one MOSFET structured to reduce floating body effects of the at least one MOSFET;

forming an oxide layer on the SOI substrate;

depositing a poly-Si layer on the oxide layer;

depositing a nitride layer on the poly-Si layer;

patterning a gate by etching portions of the poly-Si layer and the nitride layer;

forming spacers on sides of the gate;

etching portions of the oxide layer;

etching portions of an epitaxial Si layer of the SOI substrate;

etching portions of an epitaxial SiGe layer of the SOI substrate;

depositing a second epitaxial Si layer surrounding a remaining portion of the epitaxial SiGe layer, a remaining portion of the epitaxial Si layer and a remaining portion of the oxide layer;

etching a Si layer of the SOI substrate to expose the epitaxial SiGe layer;

etching portions of the epitaxial SiGe layer; and

etching portions of the second epitaxial Si layer.

9. The method of claim 8 , further comprising bonding the at least one MOSFET to a top side of another MOSFET, wherein the asymmetrical source-drain junction:

comprises a damaged pn junction; and

provides for at least one of reduced threshold voltage (Vt) variation and reduced Vt shifting with the damaged pn junction.

10. The method of claim 8 , further comprising planarizing the epitaxial SiGe layer, and wherein:

the etching portions of the oxide layer uses the nitride layer and the spacers as a mask;

the etching portions of the epitaxial Si layer of the SOI substrate uses the nitride layer and the spacers as a mask;

the etching portions of the epitaxial SiGe layer of the SOT substrate uses the nitride layer and the spacers as a mask;

flipping the at least one MOSFET; and

bonding the at least one MOSFET to another MOSFET.

11. The method of claim 10 , wherein the second epitaxial Si layer is planar with the remaining portion of the oxide layer.

12. The method of claim 11 , wherein the second epitaxial Si layer is planar with an upper surface of the remaining portion of the oxide layer.