Semiconductor package including interposer with through-semiconductor vias
The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment.
1. A semiconductor package comprising:
a contiguous organic substrate including a first group of lower interconnect pads under a first interposer, and a second group of lower interconnect pads under a second interposer;
a first group of upper interconnect pads over said first interposer, and a second group of upper interconnect pads over said second interposer;
said first interposer including a first set of through-semiconductor vias (TSVs) for electrically connecting said first group of lower interconnect pads to said first group of upper interconnect pads;
said second interposer including a second set of through-semiconductor vias (TSVs) for electrically connecting said second group of lower interconnect pads to said second group of upper interconnect pads.
2. The semiconductor package of claim 1 , further comprising a first flip-chip mounted over said first interposer, and a second flip-chip mounted over said second interposer.
3. The semiconductor package of claim 1 , wherein at least one of said first interposer and said second interposer comprises silicon.
4. The semiconductor package of claim 1 , wherein a first interposer width of said first interposer is less than a second interposer width of said second interposer.
5. The semiconductor package of claim 1 , wherein a sum of a first interposer width of said first interposer and a second interposer width of said second interposer is less than a width of said contiguous organic substrate.
6. The semiconductor package of claim 1 , wherein at least one of said first group of upper interconnect pads is directly connected to at least one of said second group of upper interconnect pads.
7. A semiconductor package comprising:
a contiguous substrate including a first group of lower interconnect pads under a first interposer, and a second interposer;
a first group of upper interconnect pads over said first interposer;
said first interposer including a first set of through-semiconductor vias (TSVs) for electrically connecting said first group of lower interconnect pads to said first group of upper interconnect pads.
8. The semiconductor package of claim 7 , further comprising a first flip-chip mounted over said first interposer.
9. The semiconductor package of claim 8 , further comprising a second flip-chip mounted over said second interposer.
10. The semiconductor package of claim 7 , wherein at least one of said first interposer and said second interposer comprises silicon.
11. The semiconductor package of claim 7 , wherein a first interposer width of said first interposer is less than a second interposer width of said second interposer.
12. The semiconductor package of claim 7 , wherein a sum of a first interposer width of said first interposer and a second interposer width of said second interposer is less than a width of said contiguous organic substrate.
13. A semiconductor package comprising:
a contiguous substrate including a first group of lower interconnect pads under a first interposer, and a second interposer;
a first group of upper interconnect pads over said first interposer, and a second group of upper interconnect pads over said second interposer;
said second interposer including through-semiconductor vias (TSVs) for providing electrically connections to said second group of upper interconnect pads.
14. The semiconductor package of claim 13 , further comprising a first flip-chip mounted over said first interposer, and a second flip-chip mounted over said second interposer.
15. The semiconductor package of claim 13 , wherein at least one of said first interposer and said second interposer comprises silicon.
16. The semiconductor package of claim 13 , wherein a first interposer width of said first interposer is less than a second interposer width of said second interposer.
17. The semiconductor package of claim 13 , wherein a sum of a first interposer width of said first interposer and a second interposer width of said second interposer is less than a width of said contiguous organic substrate.
18. The semiconductor package of claim 13 , wherein at least one of said first group of upper interconnect pads is directly connected to at least one of said second group of upper interconnect pads.