Technology mapping for threshold and logic gate hybrid circuits
View Patent ↗A method of mapping threshold gate cells into a Boolean network is disclosed. In one embodiment, cuts are enumerated within the Boolean network. Next, a subset of the cuts within the Boolean network that are threshold is identified. To minimize power, cuts in the subset of the cuts are selected.
1. A method of mapping threshold gate cells into a Boolean network called a hybridization, comprising:
enumerating cuts within the Boolean network;
representing, using a computer, a Boolean function of each of the cuts with at least a differential mode threshold logic gate using disjoint Boolean function based decomposition for threshold functions; and
selecting a subset of the cuts to use in order to minimize power or area.
2. The method of claim 1 wherein one or more of the cuts within the Boolean network are rooted at a flipflop.
3. The method of claim 1 wherein representing the Boolean function of each of the cuts comprises replacing the cuts with the at least the differential mode threshold logic gate using backward replacement.
4. The method of claim 1 wherein representing the Boolean function of each of the cuts comprises replacing the cuts with the at least the differential mode threshold logic gate using forward replacement.
5. The method of claim 1 wherein one or more of the cuts within the Boolean network is rooted at a Boolean gate.
6. The method of claim 1 wherein for each of the cuts, replacement of the each of the cuts leads to addition of a flipflop, wherein the flipflop, along with a fanin logic cone for the flipflop, is recursively hybridizable.
7. The method of claim 1 wherein each of the cuts is at least partially implementable with a threshold function.
8. The method of claim 1 further comprising identifying a threshold function by performing Integer Linear Programming (ILP).