Package substrate, module and electric/electronic devices using the same

1. A package substrate comprising:

a first conductive layer having plural first terminal pattern portions connected to a semiconductor part loaded on a first principal surface through plural first external connection conductors, wherein the first conductive layer is disposed on the first principal surface;

a second conductive layer having plural second terminal patterns connected to a system substrate mounted on a second principal surface opposite to the first principal surface through a second external connection conductor, wherein the second conductive layer is disposed on the second principal surface;

an intermediate conductive layer formed between the first conductive layer and the second conductive layer;

a first interlayer insulating layer disposed between the first conductive layer and the intermediate conductive layer;

a second interlayer insulating layer disposed between the second conductive layer and the intermediate conductive layer; and

a first plurality of interlayer connection conductors disposed in the first interlayer insulating layer such that the first plurality of interlayer connection conductors pierce through the first interlayer insulating layer;

a second plurality of interlayer connection conductors disposed in the second interlayer insulating layer such that the second plurality of interlayer connection conductors pierce through the second interlayer insulating layer, wherein the first plurality of interlayer connection conductors and the second plurality of interlayer connection conductors electrically connect the first conductive layer and the second conductive layer, and

wherein a first portion of the first plurality of interlayer connection conductors having high resistance are positioned corresponding to a central portion area of a loading area on which the semiconductor part is loaded and between a second portion of the first plurality of interlayer connection conductors having low resistance positioned corresponding to the peripheral area outside the central portion area, and

wherein the first terminal pattern portions, the first external connection conductors, the first plurality of interlayer connection conductors, the second plurality of interlayer connection conductors, the second terminal pattern portions, and the second external connection conductor are electrically connected forming plural current paths connecting the semiconductor part and the system substrate, and wherein current paths positioned corresponding to a central portion area of a loading area on which the semiconductor part is loaded have high resistance and current paths positioned corresponding to a peripheral area outside the central portion area have low resistance.

2. The package substrate according to claim 1 ,

wherein power supply current at which the semiconductor part is driven flows in the current paths.

3. The package substrate according to claim 1 ,

wherein ground current at which the semiconductor part is driven flows in the current paths.

4. The package substrate according to claim 1 ,

wherein the current paths having high resistance comprise interlayer connection conductors having high resistance and the current paths having low resistance comprise interlayer connection conductors having low resistance.

5. The package substrate according to claim 4 , further comprising plural intermediate conductive layers, wherein interlayer insulating layers are formed between adjacent intermediate conductive layers.

6. The package substrate according to claim 5 ,

wherein the same interlayer insulating layer is the interlayer insulating layer of the second layer counted from the side of the first conductive layer.

7. The package substrate according to claim 5 ,

wherein the plural intermediate conductive layers include interlayer connection conductors positioned corresponding to the loading area and having high resistance and the plural intermediate conductive layers include interlayer connection conductors positioned corresponding to the outside area and having low resistance in part or all of the interlayer insulating layers.

8. The package substrate according to claim 7 ,

wherein the plural connection conductors positioned corresponding to the loading area have high resistance and the plural interlayer connection conductors positioned corresponding to the outside area have low resistance in at least one interlayer insulating layer counted from the side of the first conductive layer.

9. The package substrate according to claim 5 ,

wherein

the number of the connection conductors having high resistance is increased as the layer number of interlayer insulating layers is increased when counting the layer number of the interlayer insulating layers is counted from the side of the first conductive layer.

10. The package substrate according to claim 4 ,

wherein the interlayer connection conductors positioned corresponding to the loading area and the interlayer connection conductors positioned corresponding to the outside area are made of conductive materials having different resistances.

11. The package substrate according to claim 4 ,

wherein the plural interlayer connection conductors stacked for connecting between the first conductive layer and the second conductive layer are formed to have a stacked via structure.

12. The package substrate according to claim 4 ,

wherein the interlayer connection conductors comprise at least one of filled vias, hollow vias or through holes in the same interlayer insulating layer.

13. The package substrate according to claim 12 ,

wherein the interlayer connection conductors positioned corresponding to the loading area and the interlayer connection conductors positioned corresponding to the outside area have different diameters.

14. The package substrate according to claim 13 ,

wherein the interlayer connection conductors are the hollow vias or the through holes, and

the interlayer connection conductors positioned corresponding to the loading area and the interlayer connection conductors positioned corresponding to the outside area have walls having different plating thicknesses.

15. The package substrate according to claim 1 ,

wherein the second external connection conductor positioned corresponding to the loading area has high resistance and the second external connection conductor positioned corresponding to the peripheral area outside the loading area has low resistance, and

the current paths positioned corresponding to the loading area have high resistance and the current paths positioned corresponding to the peripheral area outside the loading area have low resistance.

16. The package substrate according to claim 1 ,

wherein the first external connection conductors positioned corresponding to the central portion area have high resistance and the first external connection conductors positioned corresponding to the peripheral area outside the central portion area have low resistance, and

the current paths positioned corresponding to the central portion area have high resistance and the current paths positioned corresponding to the peripheral area outside the central portion area have low resistance.

17. A module comprising:

the package substrate according to claim 1 .

18. An electric/electronic device comprising:

the package substrate according to claim 1 .