Methods of forming semiconductor constructions
Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.
1. A method of forming a semiconductor construction, comprising:
patterning a semiconductor material to form a plurality of linear segments of the semiconductor material extending upwardly from a base of the semiconductor material, the segments being spaced from one another by intervening trenches; individual linear segments comprising sidewall surfaces;
forming protective material along the sidewall surfaces;
while the protective material is along the sidewall surfaces, etching into the base to form cavities under the linear segments;
forming metal-containing lines within the cavities;
patterning each of the linear segments into a plurality of vertically-oriented transistor pedestals; the transistor pedestals extending upwardly from the metal-containing lines; the transistor pedestals forming an array comprising rows and columns; the metal-containing lines extending along columns of the array to interconnect transistor pedestals along said columns, and the metal-containing lines thus being incorporated into digit lines; the digit lines only comprising metal-containing materials; and
forming access lines extending along rows of the array to interconnect transistor pedestals along said rows.
2. The method of claim 1 further comprising forming top and bottom source/drain regions within the individual transistor pedestals, with the top and bottom source/drain regions of individual transistor pedestals being spaced from one another by channel regions within the individual transistor pedestals.
3. The method of claim 2 wherein the bottom source/drain regions are formed by implanting dopant into bottoms of the linear segments prior to forming the metal-containing lines.
4. The method of claim 2 wherein the top source/drain regions are formed by implanting dopant into tops of the transistor pedestals after forming the access lines.
5. The method of claim 1 wherein the cavities completely undercut the linear segments to convert the segments into bridges having gaps thereunder, wherein the metal-containing lines are formed along the bottoms of the bridges and do not eliminate the gaps under the bridges, and wherein the patterning of the segments into the vertically-oriented transistor pedestals comprises patterning the bridges into the vertically-oriented transistor pedestals.
6. The method of claim 5 further comprising filling the gaps under the bridges with electrically insulative material after forming the metal-containing lines, with said electrically insulative material being at least semisolid.
7. The method of claim 5 wherein gas-filled gaps remain under the metal-containing lines after forming the access lines.
8. The method of claim 1 wherein the semiconductor material comprises silicon; wherein the cavities extend only partially under the linear segments to leave silicon-containing footings under the linear segments; and further comprising converting the silicon of the silicon-containing footings into metal silicide by reacting silicon from the silicon-containing footings with metal from the metal-containing lines.
9. A method of forming a semiconductor construction, comprising:
patterning a silicon-containing material to form a plurality of linear segments of the silicon-containing material extending upwardly from a base of the silicon-containing material, the segments being spaced from one another by intervening trenches; individual linear segments comprising sidewall surfaces;
forming protective material along the sidewall surfaces;
while the protective material is along the sidewall surfaces, etching into the base to form silicon-containing footings under the linear segments;
converting the footings into metal silicide;
patterning each of the linear segments into a plurality of vertically-oriented transistor pedestals; the transistor pedestals extending upwardly from the metal silicide footings;
forming top and bottom source/drain regions within the transistor pedestals, with the top and bottom source/drain regions of individual pedestals being spaced from one another by channel regions within the individual pedestals; the transistor pedestals forming an array comprising rows and columns; the metal silicide footings extending along columns of the array to interconnect transistor pedestals along said columns; and
forming access lines extending along rows of the array to interconnect transistor pedestals along said rows, the access lines extending across the channel regions and forming gates across the channel regions.
10. The method of claim 9 wherein the metal silicide footings are utilized as digit lines extending under the array, and wherein the metal silicide of the footings is the only electrically conductive material of the digit lines under the array.
11. The method of claim 9 further comprising forming metal-containing lines on opposing sides of individual metal silicide footings to form digit lines comprising the footings in combination with the metal-containing lines.
12. The method of claim 9 wherein the protective material is electrically insulative, and remains along sidewalls of the transistor pedestals as gate dielectric.
13. The method of claim 9 further comprising removing the protective material and replacing it with gate dielectric.
14. The method of claim 1 wherein the semiconductor material comprises germanium; wherein the cavities extend only partially under the linear segments to leave germanium-containing footings under the linear segments; and further comprising reacting at least some of the germanium of the germanium-containing footings with metal.