Three dimensional (3D) fan-out packaging mechanisms
The mechanisms of forming a semiconductor device package described above provide a low-cost manufacturing process due to the relative simple process flow. By forming an interconnecting structure with a redistribution layer(s) to enable bonding of one or more dies underneath a package structure, the warpage of the overall package is greatly reduced. In addition, interconnecting structure is formed without using a molding compound, which reduces particle contamination. The reduction of warpage and particle contamination improves yield. Further, the semiconductor device package formed has low form factor with one or more dies fit underneath a space between a package structure and an interconnecting structure.
1. A semiconductor package comprising:
an interconnecting structure, wherein the interconnecting structure includes a first redistribution layer (RDL) and a second RDL spaced from the first RDL, and the interconnecting structure has a thickness equal to or less than about 30 μm;
a semiconductor die bonded to the first RDL by a first bonding structure and bonded to the second RDL by a second bonding structure, wherein the first RDL of the interconnecting structure enables fan-out connection of the semiconductor die; and
a package structure bonded to the first RDL by a third bonding structure and bonded to the second RDL by a fourth bonding structure, wherein the semiconductor die is between the package structure and the interconnecting structure.
2. The semiconductor package of claim 1 , the interconnecting structure includes conductive structures surrounded by one or more dielectric layers.
3. The semiconductor package of claim 2 , wherein the one of more dielectric layers are made of photo-sensitive polymers.
4. The semiconductor package of claim 1 , further comprising a molding layer covering the package structure, wherein a total thickness of the interconnecting structure and the package structure with the molding layer is in a range from about 350 μm to about 1050 μm.
5. The semiconductor package of claim 1 , wherein a distance between a first surface of the package structure and a second surface of the interconnecting structure is in a range from about 100 μm to about 400 μm, wherein the first surface is on a side of the package structure facing the second surface.
6. The semiconductor package of claim 1 , wherein a plurality of connecting elements are bonded to the interconnecting structure on an opposite surface from the semiconductor die and the package structure.
7. The semiconductor package of claim 1 , further comprising:
another semiconductor die adjacent to the semiconductor die, wherein the other semiconductor die is bonded to the interconnecting structure and is between the package structure and the interconnecting structure.
8. The semiconductor package claim 1 , wherein the package structure includes two or more semiconductor dies.
9. The semiconductor package of claim 1 , wherein the interconnecting structure includes a first connector for forming the first bonding structure with the semiconductor die and a second connector for forming the third bonding structure with the package structure, wherein a first width of the first connector is smaller than a second width of the second connector.
10. The semiconductor package of claim 9 , wherein the first connector and the second connector both include a barrier layer.
11. The semiconductor package of claim 9 , wherein the first connector and the second connector both include a conductive layer.
12. The semiconductor package of claim 9 , wherein the first width is in a range from about 20 μm to about 100 μm.
13. The semiconductor package of claim 9 , wherein the second width is in a range from about 100 μm to about 400 μm.
14. The semiconductor package of claim 1 , further comprising a connecting element attached to a first surface of the interconnect structure, wherein the semiconductor die is bonded to a second surface, opposite the first surface, of the interconnect structure.
15. The semiconductor package of claim 1 , further comprising a molding compound wherein the molding compound fills a space between the semiconductor die and the package structure.
16. A semiconductor package comprising:
an interconnecting structure, wherein the interconnecting structure include a redistribution layer (RDL), wherein the interconnecting structure has a thickness equal to or less than about 30 μm;
a semiconductor die bonded to the interconnecting structure by a first plurality of bonding structures, wherein the RDL of the interconnecting structure enables fan-out connection of the semiconductor die; and
a package structure bonded to the interconnecting structure by a second plurality of bonding structures, wherein the semiconductor die is placed in a space between the package structure and the interconnecting structure.
17. A semiconductor package comprising:
an interconnecting structure, wherein the interconnecting structure comprises a first redistribution layer (RDL);
a semiconductor die bonded to the first RDL by a first bonding structure having a first width; and
a package structure bonded to the first RDL by a second bonding structure having a second width different from the first width, wherein the package structure is on an opposite side of the semiconductor die from the interconnecting structure, wherein an overall height of the semiconductor package ranges from about 350 microns (μm) to about 1050 μm.
18. The semiconductor package of claim 17 , wherein the interconnecting structure further comprising a second RDL separated from the first RDL, the semiconductor die is bonded to the second RDL by a third bonding structure having the first width, and the package structure is bonded to the second RDL by a fourth bonding structure having the second width.
19. The semiconductor package of claim 18 , wherein the semiconductor die is located between the second bonding structure and the fourth bonding structure.
20. The semiconductor package of claim 17 , further comprising a molding layer, wherein the molding layer surrounds the package structure and fills a space between the semiconductor die and the interconnecting structure.