Enhancement mode GaN HEMT device
An enhancement-mode GaN transistor. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process.
1. An enhancement-mode GaN transistor, comprising:
a substrate;
transition layers;
a buffer layer comprised of a III Nitride material;
a barrier layer comprised of a III Nitride material;
drain and source contacts;
a gate III-V compound containing acceptor type dopant elements; and
a gate metal that is self-aligned with the gate III-V compound,
wherein the source contact serves as a field plate, whereby the field plate is disposed over the gate III-V compound and the field plate is at source potential.
2. The transistor of claim 1 , wherein the buffer layer is comprised of InAlGaN.
3. The transistor of claim 1 , wherein the barrier layer is comprised of InAlGaN with a larger band gap than the buffer layer.
4. The transistor of claim 1 , wherein the bottom of the gate metal and the top of the gate 111 -V compound have the same dimension, and the side walls of the gate III-V compound have an angle of about 80 to about 90 degrees.
5. The transistor of claim 1 , wherein side walls of the gate III-V compound have an angle of about 30 to about 80 degrees.
6. The transistor of claim 1 , wherein the gate metal is narrower than the gate III-V compound so that there are symmetric ledges at the top of the gate compound.
7. The transistor of claim 6 , wherein side walls of the gate III-V compound have an angle of about 80 to about 90 degrees.
8. The transistor of claim 6 , wherein side walls of the gate III-V compound are sloped having an angle of 30 to 80 degrees.
9. The transistor of claim 1 , wherein the bottom of the gate metal and the top of the gate III-V compound have the same dimension, and the bottom of the gate III-V compound contains symmetric ledges just above the barrier layer.
10. The transistor of claim 1 , wherein the gate metal is narrower than the gate III-V compound so that there are symmetric ledges at the top of the gate III-V compound, and the bottom of the gate III-V compound contains symmetric ledges just above the barrier layer.
11. The transistor of claim 1 , wherein the gate III-V compound is GaN doped with acceptor type dopants such Mg, C, Zn, Ca and the p-type dopants are activated.
12. The transistor of claim 1 , wherein the gate III-V compound is GaN doped with acceptor type dopants such Mg, C, Zn, Ca and the p-type dopants are compensated with hydrogen.
13. The transistor of claim 1 , wherein the gate III-V compound contains an AlGaN layer and a GaN layer doped with acceptor type dopants such as Mg, C, Zn, Ca.
14. The transistor of claim 1 , wherein the gate III-V compound contains an AlGaN layer and a GaN layer, the gate metal and the gate GaN are etched with a single photo mask process, and the gate AlGaN extends towards the drain due to a second photo mask process.
15. The transistor of claim 1 , wherein the gate metal is TiN.
16. The transistor of claim 1 , wherein the gate metal contains one or more refractory metals, metallic compounds and alloys, such as Ta, W, TaN, TiN, WN, WSi.
17. The transistor of claim 1 , wherein the field plate extends over the gate III-V compound and towards the drain contact.