Microelectronic devices with through-substrate interconnects and associated methods of manufacturing
Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.
1. A semiconductor device, comprising:
a semiconductor substrate;
first and second metallization layers, the second metallization layer being spaced apart from the semiconductor substrate with the first metallization layer therebetween; and
a conductive interconnect extending at least partially through the semiconductor substrate, wherein the conductive interconnect includes a first end and a second end opposite the first end, wherein the second metallization layer includes a first portion generally corresponding to the conductive interconnect and a second portion extending laterally from the first portion, and wherein the first end of the conductive interconnect is electrically coupled to the first portion of the second metallization layer, wherein the first end of the conductive interconnect includes a lateral portion that extends laterally to the first portion of the second metallization layer; and
wherein the first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer; and
wherein the semiconductor substrate includes a first side and a second side; and
the semiconductor device includes:
an insulation between the first side of the semiconductor substrate and the first metallization layer;
an integrated circuit on or in the semiconductor substrate;
a conductive link at least partially in the insulation, the conductive link being between the integrated circuit and the first metallization layer;
a dielectric between the first and second metallization layers; and
the dielectric includes a conductive via directly between the first metallization layer and the second portion of the second metallization layer;
the first end of the conductive interconnect is in direct contact with the first portion of the second metallization layer; and
a solder ball attached to the second end of the conductive interconnect at the second side of the semiconductor substrate.
2. The semiconductor device of claim 1 wherein:
the dielectric having a first surface at least proximate the first metallization layer and a second surface at least proximate the second metallization layer; and
the first end of the conductive interconnect is generally planar with the second surface of the dielectric.
3. A semiconductor device, comprising:
a semiconductor substrate;
first and second metallization layers, the second metallization layer being spaced apart from the semiconductor substrate with the first metallization layer therebetween; and
a conductive interconnect at least partially through the semiconductor substrate, wherein the conductive interconnect includes a first end and a second end opposite the first end, wherein the second metallization layer includes a first portion generally corresponding to the conductive interconnect and a second portion extending laterally from the first portion, and wherein the first end of the conductive interconnect is electrically coupled to the first portion of the second metallization layer, wherein the first end of the conductive interconnect includes a lateral portion that extends laterally to the first portion of the second metallization layer; and
wherein the first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer; and wherein:
the semiconductor device also includes a dielectric between the first and second metallization layers, the dielectric having a first surface in direct contact with the first metallization layer and a second surface in direct contact with the second portion of the second metallization layer; and
the first end of the conductive interconnect is in direct contact with the first portion of the second metallization layer.
4. A semiconductor device, comprising:
a semiconductor substrate;
a first metallization layer comprising a dielectric material and conductive material;
a second metallization layer spaced apart from the semiconductor substrate by at least the first metallization layer; and
a conductive interconnect having a first end portion and a second end portion opposite the first end portion, the first end portion including a lateral portion extending laterally to a first portion of the second metallization layer, the second end portion extending at least partially through the semiconductor substrate, wherein the conductive interconnect is electrically connected to the first metallization layer via the second metallization layer, wherein the first portion of the second metallization layer is generally electrically connected to the first end portion of the conductive interconnect and a second portion of the second metallization layer is extending laterally from the first portion; and wherein:
the semiconductor substrate includes a fist side, a second side, and an aperture extending at least partially between the first and second sides;
the second metallization layer includes a first metallization surface opposite a second metallization surface; and
the semiconductor device also includes:
an insulation between the first side of the semiconductor substrate and the first metallization layer;
an integrated circuit on or in the semiconductor substrate;
a conductive link at least partially in the insulation, the conductive link being between the integrated circuit and the first metallization layer;
a dielectric between the first and second metallization layer; and
the dielectric includes a conductive via directly between the first metallization layer and the second metallization layer;
the conductive interconnect includes:
a first section of a conductive material in the aperture;
a second section of the conductive material external to the aperture;
the second section of the conductive material extending laterally on the first section; and
a solder ball attached to the second end of the conductive interconnect at the second side of the semiconductor substrate.
5. A semiconductor device, comprising:
a semiconductor substrate;
a first metallization layer comprising a dielectric material and a conductive material;
a second metallization layer spaced apart from the semiconductor substrate by at least the first metallization layer; and
a conductive interconnect having a first end portion and a second end portion opposite the first end portion, the first end portion including a lateral portion extending laterally to a fist portion of the second metallization layer, the second end portion extending at least partially through the semiconductor substrate, wherein the conductive interconnect is electrically connected to the first metallization layer via the second metallization layer, wherein the first portion of the second metallization layer is generally electrically connected to the first end portion of the conductive interconnect and a second portion of the second metallization layer is extending laterally from the first portion; and wherein:
the semiconductor device also includes a dielectric between the first and second metallization layers the dielectric having a first surface and a second surface opposite the first surface, the second surface being in direct contact with the second metallization layer;
the dielectric includes a first conductive via and a second conductive via spaced apart from the first conductive via;
the first conductive via is directly between the first metallization and the second metallization layer; and
the second conductive via is directly between the second metallization layer and the conductive interconnect.
6. The semiconductor device of claim 1 wherein the lateral portion extends over the first portion of the second metallization layer.
7. The semiconductor device of claim 3 wherein the lateral portion extends over the first portion of the second metallization layer.
8. The semiconductor device of claim 4 wherein the lateral portion extends over the first portion of the second metallization layer.