Electronic device packages having bumps and methods of manufacturing the same
An electronic device package includes a bump having a post disposed on a contact portion of a semiconductor chip and an enlarged portion laterally protruded from an upper portion of the post; an interconnection portion having a locking portion that substantially surrounds the enlarged portion and an upper sidewall of the post; and a dielectric layer substantially surrounding the bump and the locking portion to separate the interconnection portion from the semiconductor chip.
1. An electronic device package comprising:
a semiconductor chip mounted on a bottom dielectric layer;
a bump having a post disposed on a contact portion of the semiconductor chip and an enlarged portion laterally protruded from an upper portion of the post;
a dielectric layer embedding the semiconductor chip and exposing the enlarged portion of the bump and an upper sidewall of the post; and
an interconnection portion formed on the dielectric layer and having a locking portion and a connection portion,
wherein the locking portion penetrates a portion of the dielectric layer to substantially surrounds the enlarged portion of the bump and the upper sidewall of the post and the connecting portion is formed on a surface of the dielectric layer and is extended from the locking portion to serve as a circuit interconnection line.
2. The electronic device package of claim 1 , wherein the bump including the post and the enlarged portion have a substantially hammer-shaped configuration.
3. The electronic device package of claim 1 , wherein the bump includes a first metal material and the locking portion of the interconnection portion includes a second metal material different from the first metal material.
4. The electronic device package of claim 1 , wherein the bump includes gold or copper and the locking portion of the interconnection portion includes copper.
5. The electronic device package of claim 1 , further comprising:
a through via penetrating the dielectric layer and the bottom dielectric layer and connecting to the interconnection portion.