Lateral double-diffused metal oxide semiconductor (LDMOS) transistors
View Patent ↗Methods of making, structures, devices, and/or applications for lateral double-diffused metal oxide semiconductor (LDMOS) transistors are disclosed. In one embodiment, an LDMOS transistor can include: (i) an n-doped deep n-well (DNW) region on a substrate; (ii) a gate oxide and a drain oxide between a source region and a drain region of the LDMOS transistor, the gate oxide being adjacent to the source region, the drain oxide being adjacent to the drain region; (iii) a conductive gate over the gate oxide and a portion of the drain oxide; (iv) a p-doped p-body region in the source region; (v) an n-doped drain region in the drain region; (vi) a first n-doped n+ region and a p-doped p+ region adjacent thereto in the p-doped p-body region of the source region; and (vii) a second n-doped n+ region in the drain region.
1. A lateral double-diffused metal oxide semiconductor (LDMOS) transistor, comprising:
a) an n-doped deep n-well (DNW) region on a substrate;
b) a field oxide (FOX) for isolation of the LDMOS transistor, wherein the FOX comprises a first local oxidation of silicon (LOCOS);
c) a gate oxide and a drain oxide between a source region and a drain region of the LDMOS transistor, the gate oxide being adjacent to the source region, the drain oxide being adjacent to the drain region, wherein the drain oxide comprises a second LOCOS that is different than the first LOCOS such that a thickness of the drain oxide is different than a thickness of the FOX;
d) a conductive gate over the gate oxide and a portion of the drain oxide;
e) a p-doped p-body region in the source region;
f) an n-doped drain region in the drain region, the n-doped drain region ending under the drain oxide;
g) a first n-doped n+ region and a p-doped p+ region adjacent thereto in the p-doped p-body region of the source region; and
h) a second n-doped n+ region in the drain region.
2. The LDMOS transistor of claim 1 , wherein the FOX is positioned adjacent to the drain region.
3. The LDMOS transistor of claim 1 , wherein the thickness of the drain oxide is less than the thickness of the FOX.
4. The LDMOS transistor of claim 3 , wherein the thickness of the drain oxide is about 1000 Å, and the thickness of the FOX is about 4000 Å.
5. The LDMOS transistor of claim 1 , wherein the drain oxide comprises at least one of: nitride and a high-K dielectric material.
6. The LDMOS transistor of claim 1 , further comprising an n-doped source link (NSL) region in the p-doped p-body region.
7. The LDMOS transistor of claim 6 , wherein the NSL region overlaps at least a portion of the first n-doped n+ region and the p-doped p+ region in the source region.
8. The LDMOS transistor of claim 1 , wherein the drain oxide extends a predetermined distance laterally beyond a drain side edge of the conductive gate.
9. The LDMOS transistor of claim 1 , wherein a predetermined spacing separates the second n-doped n+ region from a drain side edge of the conductive gate.
10. The LDMOS transistor of claim 1 , wherein the DNW region comprises an n-doped epitaxial layer on the substrate, the substrate being a p-doped substrate.
11. A lateral double-diffused metal oxide semiconductor (LDMOS) transistor, comprising:
a) an n-doped deep n-well (DNW) region on a substrate;
b) a field oxide (FOX) for isolation of the LDMOS transistor, wherein the FOX comprises a first local oxidation of silicon (LOCOS);
c) a gate oxide and a drain oxide between a source region and a drain region of the LDMOS transistor, the gate oxide being adjacent to the source region, the drain oxide being adjacent to the drain region, wherein the drain oxide comprises a second LOCOS that is different than the first LOCOS such that a thickness of the drain oxide is different than a thickness of the FOX;
d) a conductive gate over the gate oxide and a portion of the drain oxide;
e) an n-doped n-body region in the source region;
f) a p-doped drain region in the drain region, the p-doped drain region ending under the drain oxide;
g) a first p-doped p+ region and an n-doped n+ region adjacent thereto in the n-doped n-body region of the source region; and
h) a second p-doped p+ region in the drain region.
12. The LDMOS transistor of claim 11 , further comprising a p-doped source link (PSL) region in the n-doped n-body region, wherein the PSL region overlaps at least a portion of the first p-doped p+ region and the n-doped n+ region in the source region.
13. The LDMOS transistor of claim 12 , wherein the n-doped n-body region and the PSL region are implanted using a same mask.
14. The LDMOS transistor of claim 11 , wherein the FOX is positioned adjacent to the drain region.
15. The LDMOS transistor of claim 11 , wherein the thickness of the drain oxide is less than the thickness of the FOX.
16. The LDMOS transistor of claim 15 , wherein the thickness of the drain oxide is about 1000 Å, and the thickness of the FOX is about 4000 Å.
17. The LDMOS transistor of claim 11 , wherein the drain oxide comprises at least one of: nitride and a high-K dielectric material.
18. The LDMOS transistor of claim 11 , wherein the drain oxide extends a predetermined distance laterally beyond a drain side edge of the conductive gate.
19. The LDMOS transistor of claim 11 , wherein a predetermined spacing separates the second p-doped p+ region from a drain side edge of the conductive gate.
20. The LDMOS transistor of claim 11 , wherein the DNW region comprises an n-doped epitaxial layer on the substrate, the substrate being a p-doped substrate.