Semiconductor device with buried bit line and method for fabricating the same
A semiconductor device includes trenches defined in a substrate, buried bit lines partially filling the trenches, a first source/drain layer filling remaining portions of the trenches on the buried bit lines, stack patterns having a channel layer and a second source/drain layer stacked therein and bonded to the first source/drain layer, wherein the channel layer contacts with the first source/drain layer, and word lines crossing with the buried bit lines and disposed adjacent to sidewalls of the channel layer.
1. A semiconductor device comprising:
trenches defined in a substrate;
buried bit lines partially filling the trenches;
a first source/drain layer filling remaining portions of the trenches on the buried bit lines;
stack patterns having a channel layer and a second source/drain layer stacked therein and bonded to the first source/drain layer, wherein the channel layer contacts with the first source/drain layer; and
word lines crossing with the buried bit lines and disposed adjacent to sidewalls of the channel layer.
2. The semiconductor device according to claim 1 , wherein the substrate includes a dielectric layer formed thereon, and the trenches are defined in the dielectric layer.
3. The semiconductor device according to claim 1 , further comprising:
a punch-through preventing layer formed in the substrate; and
a dielectric layer formed on surfaces of the trenches.
4. The semiconductor device according to claim 3 , wherein the trenches are defined in the punch-through preventing layer.
5. The semiconductor device according to claim 1 , wherein a surface of the first source/drain layer and a surface of the substrate are flush with each other.
6. The semiconductor device according to claim 1 , wherein the stack patterns are pillar type patterns are disposed at intersections of the word lines with the buried bit lines.
7. The semiconductor device according to claim 6 , wherein the word lines extend in one direction and surround the channel layer of the stack patterns.
8. The semiconductor device according to claim 6 , wherein the first source/drain layer is disposed between the stack patterns and the buried bit lines at the intersections.
9. The semiconductor device according to claim 8 , further comprising:
a dielectric layer filled in remaining portions of the trenches between portions of the first source/drain layer on the buried bit lines.
10. The semiconductor device according to claim 1 , further comprising:
a gate dielectric layer interposed between the channel layer and the word lines.
11. The semiconductor device according to claim 10 , wherein the gate dielectric layer extends to lower surfaces of the word lines.