Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device. A capping layer is selectively formed on the metal contact structure, and an interlayer dielectric material is deposited over the capping layer. A metal hard mask is deposited and patterned over the interlayer dielectric material to define an exposed region of the interlayer dielectric material. The method etches the exposed region of the interlayer dielectric material to expose at least a portion of the capping layer. The method includes removing the metal hard mask with an etchant while the capping layer physically separates the metal contact structure from the etchant. A metal is deposited to form a conductive via electrically connected to the metal contact structure through the capping layer.
1. A method for fabricating integrated circuits, the method comprising: forming a metal structure including a first metal over a semiconductor substrate; selectively depositing a capping layer on the metal structure; forming a metal pattern over the capping layer, wherein the first metal and the metal pattern comprise the same metal, TiN (Titanium Nitride); forming an aperture to the capping layer using the metal pattern as a mask; and removing the metal pattern with an etchant.
2. The method of claim 1 wherein depositing a capping layer comprises selectively depositing an electroless plated capping layer.
3. The method of claim 1 wherein depositing a capping layer comprises depositing an electroless plated capping layer having a thickness of about 2 nanometers (nm) to about 5 nm.
4. The method of claim 1 further comprising:
depositing a passivation layer on the capping layer; and
depositing an interlayer dielectric material on the passivation layer, wherein forming a metal pattern over the capping layer comprises forming a metal pattern over the interlayer dielectric material.
5. The method of claim 1 wherein forming a metal structure over a semiconductor substrate comprises:
forming a device over the semiconductor substrate;
depositing a dielectric material over the device;
etching a contact opening through the dielectric material to expose the device; and
filling the contact opening with metal to form the metal structure in electrical contact with the device.
6. The method of claim 1 further comprising filling the aperture to form a conductive via electrically connected to the metal structure.
7. The method of claim 1 wherein depositing the capping layer on the metal structure comprises selectively depositing the capping layer on the metal structure.
8. The method of claim 1 further comprising:
depositing a passivation layer on the capping layer, wherein forming a metal pattern over the capping layer comprises forming a metal pattern over the passivation layer.
9. A method for fabricating integrated circuits, the method comprising:
forming a metal structure over a semiconductor substrate;
depositing a capping layer having a thickness of about 2 nanometers (nm) to about 5 nm on the metal structure;
forming a metal pattern over the capping layer;
forming an aperture to the capping layer using the metal pattern as a mask; and
removing the metal pattern with an etchant.
10. The method of claim 9 wherein forming a metal structure over a semiconductor substrate comprises forming a metal structure comprising a barrier metal over a semiconductor substrate, and wherein the barrier metal and the metal pattern comprise the same metal.
11. The method of claim 10 wherein the first metal and the metal pattern are titanium nitride.
12. The method of claim 11 wherein removing the metal pattern with an etchant comprises removing the metal pattern with hydrogen peroxide, and wherein the capping layer physically separates the first metal from the hydrogen peroxide.
13. The method of claim 9 wherein depositing a capping layer comprises selectively depositing an electroless plated capping layer.
14. The method of claim 9 further comprising:
depositing a passivation layer on the capping layer, wherein forming a metal pattern over the capping layer comprises forming a metal pattern over the passivation layer.
15. The method of claim 14 further comprising:
depositing an interlayer dielectric material on the passivation layer, wherein forming a metal pattern over the capping layer comprises forming a metal pattern over the interlayer dielectric material.
16. The method of claim 9 further comprising filling the aperture to form a conductive via electrically connected to the metal structure.
17. A method for fabricating integrated circuits, the method comprising:
forming a metal structure over a semiconductor substrate;
depositing a capping layer on the metal structure;
depositing a passivation layer on the capping layer;
forming a metal pattern over the passivation layer;
forming an aperture to the capping layer using the metal pattern as a mask; and
removing the metal pattern with an etchant.
18. The method of claim 17 wherein depositing a capping layer comprises selectively depositing an electroless plated conductive layer.
19. The method of claim 17 further comprising depositing an interlayer dielectric material on the passivation layer, wherein forming a metal pattern over the capping layer comprises forming a metal pattern over the interlayer dielectric material.