IP Library Granted Patent US 8,932,935
Granted Patent B2
US 8,932,935 · App. 12/952,240 · Granted Jan 13, 2015

Forming three dimensional isolation structures

Inventors: Enzo Carollo (Montecchio Prec., IT); Marcello Mariani (Milan, IT); Sara Marelli (Cantù, IT); Luca Di Piazza (Milan, IT)
Assignee: Micron Technology, Inc.
H01L21/76224
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Quick Facts
Patent No.
US 8,932,935
App. No.
12/952,240
Granted
Jan 13, 2015
Kind
B2
Abstract

A three dimensional shallow trench isolation structure including sets of parallel trenches extending in two perpendicular directions may be formed by depositing a conformal deposition in a first set of parallel trenches, oxidizing the second set of trenches to enable selective deposition in said second set of trenches and then conformally depositing in said second set of trenches. In some embodiments, only one wet anneal, one etch back, and one high density plasma chemical vapor deposition step may be used to fill both sets of trenches.

Claims (23)

1. A method comprising:

forming a first plurality of parallel trenches extending in a first direction;

conformally depositing a dielectric in said first plurality of parallel trenches;

forming a second plurality of generally parallel trenches in a second direction perpendicular to said first direction;

treating said second plurality of generally parallel trenches, after said conformally depositing a dielectric in said first plurality of parallel trenches, to encourage selective deposition in said second plurality of generally parallel trenches; and

conformally and selectively depositing a dielectric material in said second plurality of generally parallel trenches after said treating the second plurality of generally parallel trenches.

2. The method of claim 1 including treating said second plurality of generally parallel trenches by oxidizing said second plurality of generally parallel trenches.

3. The method of claim 1 including etching back dielectric in said first plurality of parallel trenches and second plurality of generally parallel trenches at the same time.

4. The method of claim 3 including etching back to form third trenches with tapered sidewalls in said first and second directions.

5. The method of claim 4 including forming said third trenches through a layer over a semiconductor substrate and protecting said semiconductor substrate using the tapered sidewalls of said third trenches.

6. The method of claim 5 including depositing a high density plasma chemical vapor deposition oxide in said third trenches in the first and second directions at the same time.

7. The method of claim 1 including performing only one anneal for said conformal depositions in said trenches in said first and second directions.

8. The method of claim 1 including selectively depositing a dielectric in said trenches in said first and second directions and using only one etch back, one wet anneal, and one high density plasma chemical vapor deposition to fill said trenches.

9. A method comprising:

filling a first plurality of parallel trenches in a first direction;

forming a second plurality of parallel trenches in a second direction perpendicular to said first direction; and

selectively depositing a dielectric in said second plurality of parallel trenches.

10. The method of claim 9 including treating said second plurality of parallel trenches after depositing a dielectric in said first plurality of parallel trenches to encourage selective deposition in said second plurality of parallel trenches.

11. The method of claim 10 wherein treating includes oxidizing said second plurality of parallel trenches.

12. The method of claim 9 including etching back a dielectric in said first and second plurality of parallel trenches at the same time.

13. The method of claim 12 including etching back to form third trenches with tapered sidewalls in said dielectric in first and second plurality of parallel trenches.

14. The method of claim 13 including forming said third trenches through a layer over a semiconductor substrate and protecting said semiconductor substrate using the tapered sidewalls of said third trenches.

15. The method of claim 14 including depositing a high density plasma chemical vapor deposition oxide in said third trenches at the same time.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2011
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027126/0176 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 23, 2010
From: CAROLLO, ENZO; MARIANI, MARCELLO; MARELLI, SARA; DI PIAZZA, LUCA
To: MICRON TECHNOLOGY, INC.
Reel/Frame 025394/0844 →
Continuity (1)
Related Publication 20120126374A1 · May 24, 2012