IP Library › Granted Patent US 8,941,157
Granted Patent B2
US 8,941,157 · App. 14/251,210 · Granted Jan 27, 2015

Semiconductor device and method for fabricating the same

Inventors: Hyung-Hwan Kim (Gyeonggi-do, KR); Seong-Su Lim (Gyeonggi-do, KR); Sung-Eun Park (Gyeonggi-do, KR); Seung-Seok Pyo (Gyeonggi-do, KR); Min-Cheol Kang (Gyeonggi-do, KR)
Assignee: SK Hynix Inc.
H01L29/0649H01L21/7682H01L21/76897H01L23/5222H01L23/53295H01L27/10855H01L27/10885
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Quick Facts
Patent No.
US 8,941,157
App. No.
14/251,210
Granted
Jan 27, 2015
Kind
B2
Abstract

A semiconductor device includes a plurality of first conductive patterns separated by a damascene pattern, a second conductive pattern buried in the damascene pattern, and a spacer including an air gap between the second conductive pattern and the first conductive patterns.

Claims (13)

1. A semiconductor device, comprising:

a plurality of first conductive patterns separated by a damascene pattern;

a second conductive pattern buried in the damascene pattern; and

a spacer comprising an air gap between the second conductive pattern and the first conductive patterns,

wherein the spacer further comprises a first spacer and a second spacer, and the air gap is disposed between the first spacer and the second spacer,

wherein the first spacer comprises a silicon nitride layer and the second spacer comprises an oxide layer.

2. The semiconductor device of claim 1 , further comprising:

a capping layer configured to hermetically seal an upper portion of the air gap.

3. The semiconductor device of claim 1 , wherein the spacer further comprises a silicon nitride layer.

4. The semiconductor device of claim 1 , wherein the oxide layer comprises a silicon oxide layer or a tungsten oxide layer.

5. The semiconductor device of claim 1 , wherein the first conductive patterns comprise storage node contact plugs, and the second conductive pattern comprises a bit line.

6. The semiconductor device of claim 5 , wherein the storage node contact plugs comprise a polysilicon layer or a tungsten layer.

7. The semiconductor device of claim 1 , wherein the spacer further comprises a bottom surface that extends underneath the second conductive pattern.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 26, 2014
From: KIM, HYUNG-HWAN; LIM, SEONG-SU; PARK, SUNG-EUN; PYO, SEUNG-SEOK; KANG, MIN-CHEOL
To: SK HYNIX INC.
Reel/Frame 034273/0411 →
Priority Claims (1)
KR 10-2010-0140493 · Dec 31, 2010 · national
Continuity (2)
Division 13101424 · May 5, 2011
Related Publication 20140217545A1 · Aug 7, 2014