Word line driver circuits and methods for SRAM bit cell with reduced bit line pre-charge voltage
A memory device comprising a plurality of static random access memory (SRAM) bit cells, and a word line driver coupled to provide a word line signal to the bit cells. The word line driver receives a global word line signal that remains active while the word line signal is asserted and subsequently de-asserted, and the word line signal is coupled between a positive supply voltage (VDD) and a supply voltage below ground (VN).
1. A memory device, comprising:
a plurality of static random access memory (SRAM) bit cells;
a word line driver coupled to provide a word line signal to the bit cells, wherein
the word line driver receives a global word line signal that remains active while the word line signal is asserted and subsequently de-asserted, and the word line signal is coupled between a positive supply voltage (VDD) and a supply voltage below ground (VN); and
a block select driver coupled to the word line driver, wherein the block select driver includes a second latch circuit configured to receive a word line clock bar signal through a third pass transistor, and output a block select bar signal that varies between the VDD and the VN.
2. The device of claim 1 , the word line driver comprising:
a first latch circuit coupled to a first current electrode of a first pass transistor, the first pass transistor includes:
a control gate coupled to the global word line signal through a second pass transistor, wherein a control gate of the second pass transistor is coupled to the VDD, and
a second current electrode connected to a block select bar signal, wherein capacitance between the control gate and the first and second current electrodes of the first pass transistor couples voltage at the control gate of the first pass transistor to a self-boosted voltage that is greater than the VDD.
3. The device of claim 2 , further comprising:
the global word line signal varies only between the VDD and a ground (VSS).
4. The device of claim 2 , further comprising:
the first pass transistor outputs the block select bar signal to the first latch circuit when the global word line signal is asserted.
5. The device of claim 1 , further comprising:
the third pass transistor coupled to receive a block select signal through a fourth pass transistor at a control gate of the third pass transistor and the word line clock bar signal at a first current electrode of the third pass transistor, and to output the block select bar signal from a second current electrode of the third pass transistor to the word line driver when the block select signal is asserted.
6. The device of claim 1 , wherein parasitic capacitance between the current electrodes and the control gate of the third pass transistor boosts voltage at the control gate of the third pass transistor to a level above the VDD.
7. The device of claim 1 , wherein the word line clock bar signal is tri-stated while the word line signal is asserted.
8. A static random access memory (SRAM) device, comprising:
a word line driver coupled to a plurality of SRAM bit cells, wherein the word line driver is configured to:
receive a global word line signal that is driven between a positive supply voltage and ground,
receive a word line clock bar signal that is driven between a positive supply voltage (VDD) and a ground voltage at one stage of operation and is tristated at another stage of operation, and
output a word line signal that varies from the VDD to a negative voltage that is less than the ground voltage.
9. The device of claim 8 , the word line driver further comprising:
a first latch circuit driven by a signal from a first current electrode of a first pass transistor, the first pass transistor includes:
a control gate coupled to the global word line signal through a second pass transistor, and
a second current electrode coupled to a block select bar signal, wherein capacitance between the control gate and the first and second current electrodes of the first pass transistor couples the voltage at the control gate to a self-boosted voltage that is greater than the VDD while the global word line signal is asserted.
10. The device of claim 9 , further comprising:
the first pass transistor outputs the block select bar signal to the first latch circuit when the first pass transistor is conducting.
11. The device of claim 8 , further comprising:
a block select driver coupled to the word line driver, wherein the block select driver comprises a second latch circuit configured to receive a word line clock bar signal through a third pass transistor, and output a block select bar signal that varies between the VDD and a negative voltage below ground.
12. The device of claim 11 , further comprising:
the third pass transistor coupled to receive a block select signal at a control gate through a fourth pass transistor and the word line clock bar signal at a first current electrode, and to output the block select bar signal through a second current electrode to the word line driver when the block select signal is asserted.
13. The device of claim 11 , wherein the second and fourth pass transistors are one of a group consisting of: a low threshold voltage device and a depletion device.
14. The device of claim 11 , wherein the word line clock bar signal is tri-stated while the word line signal is asserted.
15. A method for operating a static random access memory (SRAM) memory device, comprising:
asserting a block select signal in a block select driver;
asserting a global word line signal in a word line driver when the block select signal is asserted;
asserting a word line clock bar signal in the block select driver after the block select signal and global word line signals are asserted, the global word line signal being driven between only a positive supply voltage signal (VDD) and ground, and the word line clock bar signal being driven between the VDD and the ground during one stage of operation and being tristated during another stage of operation; and
outputting a word line signal to a bit cell, the word line signal varies between the VDD and a negative voltage signal below ground.
16. The method of claim 15 , further comprising:
receiving the block select signal at a control gate of a first pass transistor through a second pass transistor and the word line clock bar signal at a first current electrode of the first pass transistor and outputting a block select bar signal through a second current electrode of the first pass transistor to a latch circuit; and
latching the block select bar signal to generate the word line signal.
17. The method of claim 16 , wherein:
the second pass transistor is one of a group consisting of a low threshold voltage device and a depletion device.
18. The method of claim 15 , further comprising:
tristating the word line clock bar signal while the word line signal is asserted.
19. The method of claim 15 , wherein the word line signal varies only between the VDD and the negative voltage signal below ground.