Enhancement-mode HFET circuit arrangement having high power and a high threshold voltage
A circuit includes input drain, source and gate nodes. The circuit also includes a group III nitride enhancement-mode HFET having a source, drain and gate and a voltage shifter having a first terminal connected to the gate of the enhancement mode HFET at a common junction. The circuit also includes a load resistive element connected to the common junction. The drain of the enhancement-mode HFET serves as the input drain node, the source of the enhancement-mode HFET serves as the input source node and a second terminal of the voltage shifter serves as the input gate node.
1. A monolithically integrated enhancement-mode HFET arrangement, comprising:
a group III nitride enhancement-mode HFET that includes:
a substrate;
a first active layer disposed over the substrate;
a second active layer disposed over the first active layer, wherein the second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer;
a gate that extends into the second active layer; and
a source and drain disposed over the second active layer;
a gate bus electrically coupled to the gate of the enhancement-mode HFET;
a voltage shifter monolithically integrated with the enhancement-mode HFET, said voltage shifter having a first terminal electrically coupled to the gate bus of the enhancement mode HFET;
a load resistive element monolithically integrated with the enhancement-mode HFET and the voltage shifter, the load resistive element being electrically coupled to the gate bus; and
wherein the drain of the enhancement-mode HFET serves as an input drain node of the monolithically integrated enhancement-mode HFET, the source of the enhancement-mode HFET serves as an input source node of the monolithically integrated enhancement-mode HFET and a second terminal of the voltage shifter serves as an input gate node of the monolithically integrated enhancement-mode HFET.
2. The monolithically integrated enhancement-mode HFET arrangement of claim 1 further comprising at least one metallization interconnect layer electrically coupling the enhancement-mode HFET, the voltage shifter and the enhancement-mode HFET to the gate bus.
3. The monolithically integrated enhancement-mode HFET of claim 1 wherein the group III nitride includes GaN.
4. The monolithically integrated enhancement-mode HFET of claim 1 wherein the enhancement-mode HFET is a low threshold voltage HFET.
5. The monolithically integrated enhancement-mode HFET of claim 1 wherein the voltage shifter comprises at least one diode.
6. The monolithically integrated enhancement-mode HFET of claim 1 wherein the voltage shifter comprises a plurality of Schottky diodes.
7. The monolithically integrated enhancement-mode HFET of claim 1 wherein the load resistive element comprises a resistor.
8. The monolithically integrated enhancement-mode HFET of claim 1 wherein the load resistive element comprises a transistor.
9. The monolithically integrated enhancement-mode HFET of claim 8 wherein the transistor comprises a depletion mode HFET having its gate shorted to its source.
10. The monolithically integrated enhancement-mode HFET of claim 9 wherein the depletion mode HFET comprises:
a substrate;
a first active layer disposed over the substrate;
a second active layer disposed on the first active layer, the second active layer having a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer;
a recessed gate that extends through the second active layer; and
a source, gate and drain contact disposed over the second active layer.
11. The monolithically integrated enhancement-mode HFET of claim 1 wherein the voltage shifter comprises at least one transistor.
12. The monolithically integrated enhancement-mode HFET of claim 11 wherein the at least one transistor comprises a second group III enhancement mode HFET.
13. The monolithically integrated enhancement-mode HFET of claim 12 wherein the second group III enhancement mode HFET has its gate and source shorted to ground.
14. The monolithically integrated enhancement-mode HFET of claim 12 wherein the second group III enhancement mode HFET has a drain connected to the drain of the enhancement mode HFET and a source connected to the gate of the enhancement mode HFET.
15. The monolithically integrated enhancement-mode HFET of claim 1 further comprising a fourth input node, wherein a terminal of the load resistive element serves as the fourth input node.
16. A circuit, comprising:
input drain, source and gate nodes;
a group III nitride enhancement-mode HFET having a source, drain and gate;
a voltage shifter having a first terminal connected to the gate of the enhancement mode HFET at a common junction;
a transistor connected to the common junction;
wherein the drain of the enhancement-mode HFET serves as the input drain node, the source of the enhancement-mode HFET serves as the input source node and a second terminal of the voltage shifter serves as the input gate node; and
wherein the transistor comprises a depletion mode HFET.
17. The circuit of claim 16 wherein the depletion mode HFET is a group III nitride depletion mode HFET.
18. The circuit of claim 17 wherein the group III nitride depletion mode HFET comprises:
a substrate;
a first active layer disposed over the substrate;
a second active layer disposed on the first active layer, the second active layer having a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer;
a recessed gate that extends through the second active layer; and
a source, gate and drain contact disposed over the second active layer.