Gate-all-around nanowire MOSFET and method of formation
A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.
1. An apparatus for a semiconductor device, comprising:
a nanowire formed on an insulator layer disposed on a substrate of semiconductor material, a first end of the nanowire being in communication with a source region and a second end of the nanowire being in communication with a drain region;
a gate positioned across and extending substantially transverse to the nanowire between the source region and the drain region, the gate comprising an electrode and spacers positioned on opposing sides of the electrode and extending substantially transverse to the nanowire; and
wherein a bottom portion of the gate surrounds a portion of the nanowire extending from the source region to the drain region, and wherein outer surfaces of the gate extend vertically downward into the insulator layer but do not extend beyond the inner faces of the spacers toward the source region and the drain region; and
wherein the gate further comprises a layer of high-k dielectric material disposed between the electrode and the nanowire and between the electrode and the spacers.
2. The apparatus of claim 1 , wherein inner facing surfaces at bottom portions of the spacers extend inward into the gate such that a bottom portion of the gate is narrower than a top portion of the gate.
3. The apparatus of claim 2 , wherein outward facing surfaces at the bottom portions of the spacers extend outward underneath the nanowires.
4. The apparatus of claim 1 , further comprising an interlayer dielectric material disposed on the source region and the drain region.