Method of manufacturing semiconductor device
View Patent ↗A method of manufacturing a semiconductor device is disclosed. In one embodiment, the method comprises: forming a gate stack on a substrate; etching the substrate on both sides of the gate stack to form C-shaped source/drain grooves; and wet-etching the C-shaped source/drain grooves to form Σ-shaped source/drain grooves. With this method, it is possible to effectively increase stress applied to a channel region, to accurately control a depth of the source/drain grooves, and to reduce roughness of side walls and bottom portions of the grooves and thus reduce defects by etching the C-shaped source/drain grooves and then further wet-etching them to form the Σ-shaped source/drain grooves.
1. A method of manufacturing a semiconductor device, comprising:
forming a gate stack on a substrate;
etching the substrate on both sides of the gate stack to form C-shaped source/drain grooves;
wet-etching the C-shaped source/drain grooves to form Σ-shaped source/drain grooves;
wherein forming the C-shaped source/drain grooves comprises forming a decrystallized region by means of implanting ions into the substrate and then dry-etching the decrystallized region.
2. The method according to claim 1 , wherein the gate stack comprises a gate dielectric layer and a gate conductor layer.
3. The method according to claim 2 ,
wherein the gate dielectric layer comprises any one of silicon oxide, silicon nitroxide, silicon nitride, and a high-K material, or any combination thereof, wherein the high-K material comprises composite layer(s) composed of any one or any combination of Al 2 O 3 , HfO 2 , a Hf based high-K material including at least one of HfSiO x , HfSiON, HfAlO x , HfTaO x , HfLaO x , HfAlSiO x , and HfLaSiO x , and a rare earth based high-K material including at least one of ZrO 2 , La 2 O 3 , LaAlO 3 , TiO 2 , and Y 2 O 3 , and
wherein the gate conductor layer comprises any one of polysilicon, amorphous silicon, metal, and metal nitride, or any combination thereof, wherein the metal comprises Al, Cu, Ti, Ta, Mo, or W, and the metal nitride comprises TiN or TaN.
4. The method according to claim 1 , wherein the implanted ions comprise Cl, C, O, F, or N.
5. The method according to claim 1 , wherein the C-shaped source/drain grooves are etched with an anisotropic wet-etching solution.
6. The method according to claim 1 , wherein after formation of the Σ-shaped source/drain grooves, the method further comprises:
epitaxially growing SiGe and/or SiC selectively in the Σ-shaped source/drain grooves to form stressed Σ-shaped source/drain regions;
forming metal silicide in and/or on the stressed source/drain regions; and
manufacturing interconnections.
7. The method according to claim 1 , wherein after formation of the gate stack, or after formation of the C-shaped source/drain grooves, or after formation of the stressed Σ-shaped source/drain regions, the method further comprises forming lightly doped source/drain extension regions and/or source/drain halo regions in the substrate on both sides of the gate stack and/or in the source/drain regions.