Device with strained layer for quantum well confinement and method for manufacturing thereof
View Patent ↗The disclosed technology relates to transistors having a strained quantum well for carrier confinement, and a method for manufacturing thereof. In one aspect, a FinFET or a planar FET device comprises a semiconductor substrate, a strain-relaxed buffer layer comprising Ge formed on the semiconductor substrate, a channel layer formed on the strain-relaxed buffer layer, and a strained quantum barrier layer comprising SiGe interposed between and in contact with the strain-relaxed buffer layer and the channel layer. The compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that a band offset of the channel layer and a band offset of the strained quantum barrier layer have opposite signs with respect to the strain-relaxed buffer layer.
1. A FinFET device comprising:
a semiconductor substrate; and
a fin-shaped structure, comprising:
a strain-relaxed buffer layer comprising Ge formed on the semiconductor substrate,
a channel layer formed on the strain-relaxed buffer layer, and
a strained quantum barrier layer comprising SiGe interposed between and in contact with the strain-relaxed buffer layer and the channel layer,
wherein the compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that a band offset of the channel layer and a band offset of the strained quantum barrier layer have opposite signs with respect to the strain-relaxed buffer layer, and
wherein the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer together form at least one of an electron-confining conduction band quantum well and a hole-confining valence band quantum well.
2. The FinFET device of claim 1 wherein the channel layer comprises Ge.
3. The FinFET device of claim 2 , wherein the device is a n-type FinFET and wherein the compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that between the strained quantum barrier layer and the channel layer there is a lattice constant mismatch of at least about 0.4%.
4. The FinFET device of claim 2 , wherein the device is a p-type FET and wherein the compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that the strained quantum barrier layer comprises a lower amount of Ge than the strain-relaxed buffer layer.
5. The FinFET device of claim 1 , wherein the strain-relaxed buffer layer and/or the channel layer further comprises Si.
6. The FinFET device of claim 1 , wherein the strain-relaxed buffer layer and/or the channel layer further comprises Sn.
7. The FinFET device of claim 1 , wherein the device is an n-type FET and wherein the channel layer comprises Si.
8. The FinFET device of claim 7 , wherein the compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that the strained quantum barrier layer comprises higher amount of Ge than the strain-relaxed buffer layer.
9. The FinFET device of claim 1 , wherein the strained quantum barrier layer has a thickness of about 3 nm to 30 nm.
10. A planar FET device comprising:
a semiconductor substrate;
a strain-relaxed buffer layer comprising Ge formed on the semiconductor substrate;
a channel layer comprising Ge on the strain-relaxed buffer layer; and
a strained quantum barrier layer comprising SiGe interposed between and in contact with the strain relaxed buffer layer and the channel layer,
wherein the compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that a band offset of the channel layer and a band offset of the strained quantum barrier layer have opposite signs with respect to the strain-relaxed buffer, and
wherein the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer together form at least one of an electron-confining conduction band quantum well or a hole-confining valence band quantum well.
11. The planar FET device of claim 10 , wherein the device is a n-type FET and wherein the compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that between the strained quantum barrier layer and the channel layer there is a lattice constant mismatch of at least about 0.4%.
12. The planar FET device of claim 10 , wherein the strain-relaxed buffer layer and/or the channel layer further comprises Si.
13. The planar FET device of claim 10 , wherein the strain-relaxed buffer layer and/or the channel layer further comprises Sn.
14. The planar FET device of claim 10 , wherein the device is a p-type FET and wherein the compositions of the strain-relaxed buffer layer, the strained quantum barrier layer and the channel layer are chosen such that the strained quantum barrier layer comprises a lower amount of Ge than the strain relaxed buffer layer.
15. The planar FET device of claim 10 , wherein the strained quantum barrier layer has a thickness of about 3 nm to 30 nm.